Cortex-M: add opt-in explicit layout lowering - #21967
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🔗 Helpful Links🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21967
Note: Links to docs will display an error until the docs builds have been completed. ❌ 3 New Failures, 1 Unrelated FailureAs of commit 17b573e with merge base 1b2838b ( NEW FAILURES - The following jobs have failed:
BROKEN TRUNK - The following job failed but were present on the merge base:👉 Rebase onto the `viable/strict` branch to avoid these failures
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This was referenced Aug 20, 2026
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Thread an experimental explicit-layout mode through the shared Edge compile configuration, AOT compiler, quantizer, tester, and pass manager while retaining legacy dim-order export as the default.
Explicit mode disables dim-order operators, converts Conv1d through the common transform, runs the common channels-last pipeline, lowers anchors to fixed _nhwc schemas, and lowers surviving boundaries to cortex_m transpose. Padding is retargeted explicitly, output dequantization remains a layout barrier, and unequal-shape add or multiply stays outside the region until separately admitted.
Package the host test harness and assert expected Cortex-M targets before planned-memory comparisons for M33 and M55.
Nine Cortex-M55 FVP cases, common-transform suites, and lintrunner.
Authored with Codex.