Cortex-M: add explicit-NHWC runtime operators

[rascani]

Add fixed-layout NHWC-logical schemas for quantized convolution, depthwise convolution, transpose convolution, average pooling, max pooling, and padding.

Each wrapper lives beside its legacy entry point and selects NHWCLogical in the shared implementation, so operator identity carries the serialized layout contract without a general-purpose runtime parameter. Register the schemas, Python reference implementations, scratch sizing, selective runner entries, and host and FVP coverage.

Harden both padding entry points by validating rank and four-element padding before indexing and by reporting the actual entry-point name.

All six explicit-NHWC cases on Cortex-M55 and Cortex-M33 FVPs, selective-runner cross-builds, and lintrunner.

Authored with Codex.

[rascani]

Stack from ghstack (oldest at bottom):

• Cortex-M: keep NHWC channel broadcasts quantized #21968
• Cortex-M: add opt-in explicit layout lowering #21967
• Cortex-M: add explicit-NHWC channel-broadcast ops #21966
• -> Cortex-M: add explicit-NHWC runtime operators #21965
• Cortex-M: share layout-aware CMSIS-NN kernels #21964
• Channels last: add the common layout pipeline #21963
• Channels last: optimize structural layout regions #21962
• Channels last: preserve metadata across op replacement #21961

[pytorch-bot]

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❌ 3 New Failures, 1 Unclassified Failure

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• pull / test-qnn-buck-build-linux / linux-job (gh)
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• pull / unittest-buck / linux / linux-job (gh)
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• pull / unittest-buck / macos / macos-job (gh)
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