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Cortex-M: share layout-aware CMSIS-NN kernels - #21964

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Cortex-M: share layout-aware CMSIS-NN kernels#21964
rascani wants to merge 2 commits into
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@rascani

@rascani rascani commented Aug 20, 2026

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Refactor convolution, depthwise convolution, transpose convolution, average pooling, and max pooling behind shared internal implementations that accept a private activation-layout mode.

Existing registered operators continue selecting the legacy NCHW-logical contract over channels-last storage. This commit changes no public schema or AOT lowering and provides the common implementation used by the following fixed-NHWC wrappers.

59 default-mode dialect tests, MobileNetV3 lowering, and unmodified main-built legacy PTEs for all five refactored operators.

Authored with Codex.

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🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/executorch/21964

Note: Links to docs will display an error until the docs builds have been completed.

❌ 3 New Failures

As of commit 643cd15 with merge base 1b2838b (image):

NEW FAILURES - The following jobs have failed:

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