instruction-scheduling

An optimized schedule for a simulated VLIW/SIMD CPU kernel executing a parallel tree traversal & custom hashing workload using Python. Achieves a 16.74x speedup (reducing CPU cycles from 18532 to 1107), surpassing the Claude Opus 4.5 baseline.

Interactive simulator for Scoreboard and Tomasulo dynamic instruction scheduling with cycle-accurate execution, hazard visualization, Gantt charts, reservation stations, and a Flutter + FastAPI interface.

Toy Compiler backend for Very Large Instruction Word processors (VLIW)