An interactive educational simulator for visualizing and comparing Scoreboard and Tomasulo's Algorithm in modern processors.
Developed for the Advanced Computer Architecture course at Amirkabir University of Technology.
The ACA Dynamic Instruction Scheduling Simulator is a cycle-accurate educational tool designed to help students understand how dynamic instruction scheduling works inside modern CPUs.
The simulator supports two of the most important scheduling algorithms:
-
Scoreboard
- Centralized hazard detection
- No register renaming
- WAR/WAW hazards cause stalls
-
Tomasulo's Algorithm
- Distributed reservation stations
- Register renaming
- Common Data Bus (CDB)
- Eliminates WAR and WAW hazards
The project provides a modern graphical interface that allows users to create custom instruction sequences, configure processor resources, execute simulations cycle-by-cycle, and visualize every stage of execution.
- Create custom instruction scheduling scenarios
- Configure functional units and execution latencies
- Built-in educational examples
- Save, edit, duplicate, and delete scenarios
- Import / Export scenarios (
.aca)
Visual timeline showing:
- Issue
- Read Operands
- Execute
- Write Back
- Waiting/Stall periods
Cycle-accurate execution table including:
| Column | Description |
|---|---|
| Issue | Instruction issue cycle |
| RO | Read operands |
| EX | Execute |
| WB | Write back |
Automatically detects:
- ✅ RAW (Read After Write)
- ✅ WAR (Write After Read)
- ✅ WAW (Write After Write)
with detailed information about dependent instructions.
Displays:
- Total execution cycles
- Number of instructions
- Average instruction latency
- IPC / Issue rate
- Functional unit utilization
Pie chart showing instruction distribution by type:
- LOAD
- STORE
- ADD
- SUB
- MUL
- DIV
When Tomasulo mode is selected, the simulator additionally displays:
- Reservation Stations
- Register Status Table
- Register Tags
- Common Data Bus (CDB) activity
Cycle-by-cycle textual execution log showing:
- Instruction issued
- Operand reads
- Execution start/end
- Write-back events
- Hazard detection
- Functional unit allocation
A synchronized CPU clock updates every simulation cycle to provide an intuitive visualization of processor timing.
The simulator supports both automatic and manual execution.
- ▶ Play
- ⏸ Pause
- ⏭ Step Forward
- ⏮ Step Backward
- 🎚 Cycle Slider
- ⚡ Clock Speed Control
Users can jump to any simulation cycle or replay the execution from any point.
| Feature | Scoreboard | Tomasulo |
|---|---|---|
| Dynamic Scheduling | ✅ | ✅ |
| Centralized Control | ✅ | ❌ |
| Reservation Stations | ❌ | ✅ |
| Register Renaming | ❌ | ✅ |
| RAW Detection | ✅ | ✅ |
| WAR Elimination | ❌ | ✅ |
| WAW Elimination | ❌ | ✅ |
| Common Data Bus (CDB) | ❌ | ✅ |
Built with Python + FastAPI
src/
├── instruction.py # Instruction parser and model
├── utils.py # Utilities and configuration loader
├── scoreboard.py # Scoreboard simulator
├── tomasulo.py # Tomasulo simulator
├── simulator.py # Simulation orchestrator
└── api.py # REST API
Built with Flutter + BLoC
lib/
├── models/
├── screens/
│ ├── onboarding/
│ ├── dashboard/
│ ├── scenario/
│ ├── simulator/
│ └── compare/
├── widgets/
├── bloc/
├── services/
└── core/
- Python 3.8+
- FastAPI
- Uvicorn
- Flutter 3.0+
git clone https://github.com/yourusername/aca_project.git
cd aca_project
pip install fastapi uvicorn python-multipart
uvicorn src.api:app --reload --host 0.0.0.0 --port 8000cd frontend
flutter pub get
flutter run- Click New Scenario
- Enter a scenario name
- Select scheduling algorithm
- Configure functional units
- Configure execution latencies
- (Optional) Configure reservation stations
- Enter assembly instructions
- Save or run the scenario
- Open a saved scenario
- Click Run Simulation
- Control execution using Play/Pause or manual stepping
- Navigate between visualization tabs
Select two scenarios and press Compare to view side-by-side comparisons of:
- Execution timeline
- Total cycles
- Performance metrics
- Hazard statistics
| Instruction | Format | Example |
|---|---|---|
| LOAD | LOAD Rd offset(Rs) |
LOAD R1 0(R2) |
| STORE | STORE Rs offset(Rbase) |
STORE R3 4(R2) |
| ADD | ADD Rd Rs1 Rs2 |
ADD R4 R1 R5 |
| SUB | SUB Rd Rs1 Rs2 |
SUB R6 R7 R8 |
| MUL | MUL Rd Rs1 Rs2 |
MUL R3 R1 R4 |
| DIV | DIV Rd Rs1 Rs2 |
DIV R8 R2 R9 |
LOAD R1 0(R2)
MUL R3 R1 R4
ADD R5 R3 R6
SUB R1 R7 R8
MUL R9 R1 R10
ADD R11 R9 R12
STORE R11 0(R13)| Method | Endpoint | Description |
|---|---|---|
GET |
/ |
Health check |
POST |
/run_simulation |
Execute a simulation |
{
"mode": "scoreboard",
"instructions": [
"LOAD R1 0(R2)",
"MUL R3 R1 R4"
],
"config": {
"registers": [
"R0",
"R1",
"R2",
"R3",
"R4",
"R5"
],
"functional_units": {
"ALU": {
"count": 2,
"latency": 2
},
"MULT": {
"count": 1,
"latency": 10
},
"LOAD_STORE": {
"count": 1,
"latency": 2
}
}
}
}LOAD R1 0(R2)
MUL R3 R1 R4
ADD R5 R3 R6
SUB R1 R7 R8
MUL R9 R1 R10
ADD R11 R9 R12
STORE R11 0(R13)Expected hazards:
- RAW ×3
- WAR ×1
- WAW ×1
MUL R1 R2 R3
ADD R4 R1 R5MUL R1 R2 R3
SUB R1 R4 R5ADD R1 R2 R3
MUL R4 R1 R5
ADD R1 R6 R7| Unit | Count | Latency | Operations |
|---|---|---|---|
| ALU | 2 | 2 | ADD, SUB, AND, OR, XOR |
| MULT | 1 | 10 | MUL, DIV |
| LOAD/STORE | 1 | 2 | LOAD, STORE |
| Functional Unit | Stations |
|---|---|
| ALU | 3 |
| MULT | 2 |
| LOAD/STORE | 2 |
pip install fastapi uvicorn python-multipart
netstat -ano | findstr :8000Verify that:
- Backend is running
- API URL is correct
- CORS is enabled
- Port 8000 is available
Ensure:
- Functional unit counts are integers
- Latencies are integers
- Configuration maps are correctly formatted
- Python
- FastAPI
- Flutter
- Dart
- flutter_bloc
- Custom Flutter Widgets
- Interactive Gantt Charts
- Data Tables
- Charts
Reza Tahmasbi
Advanced Computer Architecture Course
Amirkabir University of Technology
Summer 1405
Version 1.1
This project is intended solely for educational purposes.
All rights reserved.
For questions, bug reports, or suggestions, please contact the author through mailing: rezatahmasbi@aut.ac.ir