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frontend: Report the documented stall polarity in the inst64 events - #187

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DanielKellerM merged 1 commit into
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DanielKellerM:frontend/inst64-events
Aug 17, 2026
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frontend: Report the documented stall polarity in the inst64 events#187
DanielKellerM merged 1 commit into
pulp-platform:develfrom
DanielKellerM:frontend/inst64-events

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@DanielKellerM DanielKellerM commented Aug 13, 2026

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The Snitch cluster defines these counters explicitly, in snitch_cluster_peripheral_reg.rdl:

dma_r_stall     = 12  "Incremented whenever r_ready = 1 but r_valid = 0"
dma_w_stall     = 13  "Incremented whenever w_valid = 1 but w_ready = 0"
dma_buf_w_stall = 14  "Incremented whenever w_ready = 1 but w_valid = 0"
dma_buf_r_stall = 15  "Incremented whenever r_valid = 1 but r_ready = 0"

snitch_cluster_peripheral.sv maps each metric to the identically named dma_events_t field with no remapping, so that text is a direct contract on the field.

The two lines this removes are, verbatim, the definitions of 14 and 15 sitting in the fields for 12 and 13, where they overrode the correct assignments made earlier in the same always_comb. Removing them restores 12 and 13:

field after this PR RDL
r_stall r_ready && !r_valid whenever r_ready = 1 but r_valid = 0
w_stall !w_ready && w_valid whenever w_valid = 1 but w_ready = 0

The asymmetry that remains is the intended one: iDMA drives w_valid but r_ready, so waiting on the fabric is valid-without-ready on AW, AR and W, and ready-without-valid on R.

Why it looks like this today

Both pairs arrived in one commit (097f6140, PR #40) that flattened axi_dma_perf_counters.sv's if-guarded set-only writes over a '0 default into unconditional assignments. Under the guards the two conditions fed four separate counters; unconditional, the later pair simply clobbers the earlier one. Accidental, not a design decision.

Testbench

tb_idma_inst64_axi_copy asserted the old behaviour, so its two goldens move with the RTL in the same commit. Verified both ways with Questa:

  • with this change: TEST PASSED, rc=0
  • with either side reverted: Fatal: events.EvRStall disagrees with the AXI pins, rc=2

Worth noting that no CI job runs that testbench today: it is reachable only through make idma_sim_tb_idma_inst64_axi_copy. Without running it by hand, devel would have stayed green while shipping RTL that contradicts its own assertions.

Impact

This is a silent change to reported performance counters. Metric 13 currently counts mostly bus idle, since a registered W slice parks WREADY high; metric 12 currently reads near zero because inst64 ties rsp_ready high. Existing profiles change meaning with no version marker, so it wants a CHANGELOG line alongside #201.

No programmatic reader of these counters exists in snitch_cluster outside the RDL and its generated packages, so anyone reading them reads them against the RDL, which is to say against the corrected values.

Not done here

Renaming the two lines to buf_w_stall / buf_r_stall rather than deleting them would fix 12 and 13 and light up 14 and 15, which read constant zero before and after this PR. The cost is integrators whose dma_events_t is narrower than the cluster's, including this repo's own testbench mirror in test/frontend/idma_inst64_tb_pkg.sv, which omits both fields. Left for a follow-up rather than folded in here.

Copilot AI lite review requested due to automatic review settings August 13, 2026 09:59
@DanielKellerM
DanielKellerM requested a review from micprog as a code owner August 13, 2026 09:59

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Copilot was unable to review this pull request because the user who requested the review has reached their quota limit.

The Snitch cluster defines these counters, and it defines them explicitly:

  dma_r_stall     = 12  "Incremented whenever r_ready = 1 but r_valid = 0"
  dma_w_stall     = 13  "Incremented whenever w_valid = 1 but w_ready = 0"
  dma_buf_w_stall = 14  "Incremented whenever w_ready = 1 but w_valid = 0"
  dma_buf_r_stall = 15  "Incremented whenever r_valid = 1 but r_ready = 0"

The two lines removed here are, verbatim, the definitions of 14 and 15 sitting
in the fields for 12 and 13, where they overrode the correct assignments made
earlier in the same always_comb. Both pairs arrived in one commit that flattened
if-guarded set-only writes into unconditional ones, so the later pair silently
won. Removing them restores 12 and 13.

The asymmetry that remains is the intended one: iDMA drives w_valid but r_ready,
so waiting on the fabric is valid without ready on AW, AR and W, and ready
without valid on R.

The inst64 testbench asserted the old behaviour, so its two goldens move with
the RTL. Verified both ways: the testbench passes with this change and fails
with "events.EvRStall disagrees with the AXI pins" if either side is reverted.
@DanielKellerM
DanielKellerM force-pushed the frontend/inst64-events branch from 1ead49a to 75f489c Compare August 17, 2026 12:28
@DanielKellerM DanielKellerM changed the title frontend: Drop the overridden stall assignments in the inst64 events frontend: Report the documented stall polarity in the inst64 events Aug 17, 2026
@DanielKellerM
DanielKellerM merged commit 8c48ae8 into pulp-platform:devel Aug 17, 2026
26 checks passed
DanielKellerM added a commit to DanielKellerM/iDMA that referenced this pull request Aug 17, 2026
pulp-platform#187 landed after this entry was written. It is in Fixed, and it also gets a
line beside the incompatibilities: the counters change meaning with no version
marker, so a profile captured before the release does not compare with one
captured after.
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2 participants