test: Add an inst64 frontend testbench driven over the accelerator bus - #185
Conversation
The tightly-coupled frontend had no public testbench, so nothing exercised the DMA ISA decode, the id/status path or the datapath below it. Port the existing harness and driver, dropping the vidma-only ISA: DMOPC decodes bit-identically to the public DMINIT, so carrying it over would have launched a real zero-fill transfer and desynchronised the completion wait.
The event outputs feed downstream performance counters but nothing verified them; the testbench observed the same handshakes independently and ignored them. Compare all 26 observable fields against the pins every cycle and anchor the totals, keeping the independent sniff as the reference so a wrong counter cannot agree with itself.
7fc6f86 to
94f4013
Compare
| /// only (DMSRC/DMDST/DMSTR/DMREP/DMCPY/DMCPYI/DMSTAT). The vidma-only DMOPC/ALU/MX | ||
| /// opcodes are deliberately absent: DMOPC's encoding aliases public DMINIT and would | ||
| /// silently launch a real zero-fill transfer. |
There was a problem hiding this comment.
Remove references to vidma The vidma-only DMOPC/ALU/MX
/// opcodes are deliberately absent: DMOPC's encoding aliases public DMINIT and would
/// silently launch a real zero-fill transfer.
| /// Concrete type binding for the `idma_inst64_top` testbenches. The types mirror | ||
| /// `test/idma_inst64_lint.sv`, the elaboration-proven binding of the frontend. |
There was a problem hiding this comment.
remove this comments as they might be obsolete
| // `events_o` is exported for downstream performance counters but nothing verified it. | ||
| // Every field is a zero-latency recode of the DUT's own top-level pins, so the TB | ||
| // rebuilds the expected value from those pins and compares it per cycle. This checks | ||
| // the recode (mapping, polarity, gating, width), not the bus traffic; the geometry | ||
| // anchors below are what keep it from passing on a run where nothing happened. The | ||
| // hand-counted AR/AW sniff stays the independent source of truth and is untouched. | ||
| // | ||
| // Deliberately not checked here: obi_wr_req/obi_rd_req (a_no_obi_traffic pins both | ||
| // sides to 0, so an equality proves nothing; needs a TCDM-window TB with an OBI | ||
| // read/write mix) and the per-channel index in gen_events (NumChannels == 1). | ||
| // | ||
| // Polarity note: aw_stall/ar_stall are valid && !ready, but idma_inst64_events | ||
| // overrides its own w_stall/r_stall at lines 95/96, so w_stall is a W-side bubble | ||
| // (w_ready && !w_valid) and r_stall is !r_ready && r_valid; the earlier assignments | ||
| // are dead code. Measured gap: none of the four stall fields ever asserts here, since | ||
| // the sim memories neither backpressure nor bubble. Their equality still catches a | ||
| // polarity flip or a spurious assert, but a stuck-at-0 stall would pass; that needs a | ||
| // ready-throttling harness, not a weaker check. |
There was a problem hiding this comment.
verbose explanation, reduce to 3 o4 4 lines
| // Sentinel over the destination and its guard bands: an unwritten byte must fail | ||
| // the compare rather than accidentally match, and an overrun must be visible. | ||
| // Offsets stay non-negative; a signed offset added to a 64-bit unsigned address is | ||
| // zero-extended, not sign-extended. |
| # Tightly-coupled inst64 frontend driven over the snitch accelerator bus. | ||
| # Run with the Questa SEPP wrapper: | ||
| # make idma_sim_tb_idma_inst64_axi_copy VSIM="questa-2023.4 vsim" |
There was a problem hiding this comment.
remove comments
|
Addressed in a1612d2.
Re-verified after the edits: One thing the edits surfaced, separate from this PR: |
The goldens mirrored the RTL rather than the counter spec, so both sides read zero for the whole transfer and the four stall comparisons could not fail.
|
Note on merge order: this now expects the documented stall polarity in the event cross-check, so #187 has to land first. On today's devel RTL the goldens for Background: an audit of #187 against |
…-check" The matching RTL fix is not on devel yet; this expectation moves to the pull request that changes the polarity, so the two land together.
The tightly-coupled inst64 frontend had no public testbench. Nothing exercised the DMA ISA decode, the transfer id and status path, or the datapath below it; only syntax analysis reached those sources.
Ports the existing harness (
idma_inst64_tb_pkg,idma_inst64_drv_if,idma_inst64_base) and adds a directed AXI-to-AXI copy test driving dmsrc/dmdst/dmcpyi and polling dmstati.Verified
$finish,TEST PASSED: 4096 B copied, ar=1 aw=1 beats.payload mismatch at offset 777: expected 0xa9, got 0xbaandTEST FAILED. The TB also sentinels the destination and adds guard bands, so an unwritten byte or an overrun fails too.make idma_sim_tb_idma_inst64_axi_copygates on both a negativeError:|Fatal:grep and a positiveTEST PASSEDgrep, because Questa does not propagate$fatalto the exit code and a sim that never starts would pass a negative-only gate.Note on the port
The upstream harness builds on
DMOPC, which is not part of the public ISA. It is not merely absent:DMOPCdecodes bit-identically to the publicDMINIT, so carrying it over would have launched a real zero-fill transfer, burning a transfer id and bumpingcompleted_id, desynchronising the completion wait so it could return before the copy retired. The opcode and its callers are therefore dropped rather than stubbed. Head arguments are dropped for the same reason: the public decoder ignoresdata_argb[12:5], so passing them would be a silent no-op.