Fix: build host_build_graph orchestration on x86 hosts

[ChaoZheng109]

Why

host_build_graph runs its orchestration .so on the host CPU
(build_config: "Host runs the orchestrator to completion, populating SM +
arena, then H2Ds the image to device"), so compile_orchestration()
builds it with the bare host g++ (ToolchainType.HOST_GXX). That orch
compile unconditionally links the onboard AICPU helpers
device_time.cpp / cache_ops.cpp (added by #1236 so orch SOs using the
public AICPU helper headers resolve). Both files' bodies are
aarch64-only inline asm — mrs cntvct_el0, dc civac/cvac,
dsb, isb.

On an ARM64 runner the host g++ targets aarch64, so the asm assembled
and the latent "host is aarch64" assumption stayed hidden. #1361 made
st-onboard-a2a3 eligible for the new x86_64 runners; there the host
g++ feeds aarch64 asm to the x86 assembler and every host_build_graph
L2 test fails at compile time:

src/common/platform/onboard/aicpu/device_time.cpp:15: Error: no such instruction: `mrs %rax,cntvct_el0'
RuntimeError: Orchestration compilation failed with exit code 1

tensormap_and_ringbuffer is unaffected: its orch cross-compiles with
AARCH64_GXX and runs on the device AICPU, never through the host g++.

What

Gate the asm behind __aarch64__ and add a host-portable #else:

• device_time: derive the sys-cnt tick from std::chrono, scaled to
  the same PLATFORM_PROF_SYS_CNT_FREQ unit the DFX markers decode
  against (mirrors the existing sim variant).
• cache_ops: no-op. The host orchestrator reaches device memory only
  through driver H2D DMA (cache-coherent on x86), so the AICPU-side
  manual cache maintenance has no host-side referent.

aarch64 (device AICPU and ARM64-host orchestration) takes the exact
same code as before — zero behavior change on every currently-working
path. Only the x86 host build gains a compilable path.

Verification

• aarch64 branch compiles with native g++ (both files).
• x86 #else body verified as portable C++ (chrono + macro, no asm).
• common/platform_config.h is already on the orch include path
  (get_platform_include_dirs() → src/a2a3/platform/include).
• End-to-end x86 validation requires CI to land st-onboard-a2a3 on an
  x86_64 runner.

Note

The separate st-onboard-a5 red (/tmp/pytest-of-simpler_a5ci is not owned by the current user) is an a5-runner environment issue (stale tmp
dir), unrelated to this change.

[coderabbitai]

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📝 Walkthrough

Walkthrough

AICPU cache maintenance now has non-AArch64 no-op implementations, while system-counter timing uses a scaled std::chrono fallback outside AArch64 builds.

Changes

AICPU portability

Layer / File(s)	Summary
Cache maintenance portability src/common/platform/onboard/aicpu/cache_ops.cpp	AArch64 builds retain cache-maintenance implementations; other architectures compile no-op invalidate_range_impl and flush_range_impl functions.
System counter portability src/common/platform/onboard/aicpu/device_time.cpp	AArch64 builds read cntvct_el0; other architectures derive profiling ticks from std::chrono::high_resolution_clock and PLATFORM_PROF_SYS_CNT_FREQ.

Estimated code review effort: 2 (Simple) | ~10 minutes

Poem

A rabbit hops where cache winds blow,
On AArch64, the instructions flow.
Else they rest, quiet and still,
While clocks tick on with chrono skill.
Cross-platform paths now bloom—
Thump-thump! builds find room.

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Title check	✅ Passed	The title clearly summarizes the main change: fixing x86 host orchestration builds.
Description check	✅ Passed	The description is directly about the x86 host build failure and the AArch64 guard fix.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Linked Issues check	✅ Passed	Check skipped because no linked issues were found for this pull request.
Out of Scope Changes check	✅ Passed	Check skipped because no linked issues were found for this pull request.

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[gemini-code-assist]

Code Review

This pull request adds support for non-aarch64 platforms in AICPU cache operations and device timing. Cache maintenance operations are stubbed out as inert on non-aarch64, and get_sys_cnt_aicpu is updated to emulate the hardware timer using a host-side clock. The review feedback correctly points out that std::chrono::high_resolution_clock should be replaced with std::chrono::steady_clock to guarantee monotonicity and avoid issues with system time adjustments.

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[coderabbitai]

Actionable comments posted: 1

🤖 Prompt for all review comments with AI agents

Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.

Inline comments:
In `@src/common/platform/onboard/aicpu/device_time.cpp`:
- Line 29: Replace std::chrono::high_resolution_clock with
std::chrono::steady_clock when capturing now in the system counter tick
implementation, preserving the existing tick conversion and return behavior so
get_sys_cnt_aicpu() remains strictly monotonic like device_time_now_ticks().

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Fix all unresolved CodeRabbit comments on this PR:

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• Create a new PR with the fixes

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📥 Commits

Reviewing files that changed from the base of the PR and between cddf2b6 and 92f0dfd.

📒 Files selected for processing (2)

• src/common/platform/onboard/aicpu/cache_ops.cpp
• src/common/platform/onboard/aicpu/device_time.cpp