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Fix: add aarch64 guards for ARM64 inline assembly in AICPU files#1366

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doraemonmj wants to merge 2 commits into
hw-native-sys:mainfrom
doraemonmj:fix/x86-aarch64-guard
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Fix: add aarch64 guards for ARM64 inline assembly in AICPU files#1366
doraemonmj wants to merge 2 commits into
hw-native-sys:mainfrom
doraemonmj:fix/x86-aarch64-guard

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@doraemonmj

@doraemonmj doraemonmj commented Jul 15, 2026

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Problem

CI fails on x86_64 runners when compiling a2a3 hostbuild because files in src/common/platform/onboard/aicpu/ contain ARM64-specific inline assembly instructions that cannot be compiled on x86_64:

Error: no such instruction: `dc civac,%rax\'
Error: no such instruction: `mrs %rax,cntvct_el0`

Solution

Add #if defined(__aarch64__) guards around ARM64 inline assembly:

  • cache_ops.cpp: Wrap ARM64 cache instructions (dc civac, dc cvac, dsb, isb)
  • device_time.cpp: Wrap ARM64 mrs cntvct_el0 instruction
  • Provide empty stub implementations for x86_64 (these are onboard-only files, so the x86 path is unreachable at runtime)

Notes

  • PR ci(a2a3): run pytest/ctest directly on X64 runners, task-submit on ARM64 #1361 (cddf2b6c) worked around this issue by CI configuration (x86 runners skip compilation of ARM64 code), but that only fixes CI, not the code itself
  • This fix makes the code compilable on any architecture, following cross-platform best practices
  • The x86 stubs are unreachable at runtime since these files are only used in onboard builds

- Wrap ARM64 cache instructions (dc civac, dc cvac, dsb, isb) in
  cache_ops.cpp with #if defined(__aarch64__)
- Wrap ARM64 mrs cntvct_el0 instruction in device_time.cpp with
  #if defined(__aarch64__)
- Provide empty stub implementations for x86_64 (onboard-only,
  so x86 path is unreachable at runtime)

This fixes compilation failures on x86_64 CI runners that attempt
to compile ARM64-specific inline assembly instructions.

Closes hw-native-sys#1325
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coderabbitai Bot commented Jul 15, 2026

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Review Change Stack

📝 Walkthrough

Walkthrough

AICPU cache maintenance and system-counter access are now conditionally compiled for AArch64. Non-AArch64 builds use no-op cache functions and device_time_now_ticks() for timing.

Changes

AICPU architecture handling

Layer / File(s) Summary
Architecture-specific cache and time paths
src/common/platform/onboard/aicpu/cache_ops.cpp, src/common/platform/onboard/aicpu/device_time.cpp
AArch64 retains ARM cache and counter operations; non-AArch64 builds use no-op cache functions and a device-time fallback.

Estimated code review effort: 1 (Trivial) | ~5 minutes

Possibly related PRs

Poem

A bunny checks the guarded code,
ARM keeps its speedy road.
Other lands hop safely through,
With quiet caches and clock ticks too.
No fragile assembly blocks the way—
Hoppy builds for every day!

🚥 Pre-merge checks | ✅ 3 | ❌ 2

❌ Failed checks (2 warnings)

Check name Status Explanation Resolution
Linked Issues check ⚠️ Warning The PR only adds compile guards and fallback stubs; it does not implement the selective task timing slots or timeline behavior in #1325. Implement the timing-slot feature requirements from #1325, or remove the issue link if this PR is only meant to fix cross-architecture compilation.
Out of Scope Changes check ⚠️ Warning The architecture guards and x86 fallback are unrelated to the linked feature requirements, so they appear out of scope for #1325. Move this compilation fix to a separate PR or broaden the linked issue scope if it is intended as prerequisite work.
✅ Passed checks (3 passed)
Check name Status Explanation
Docstring Coverage ✅ Passed No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.
Title check ✅ Passed The title clearly matches the main change: adding aarch64 guards around ARM64 inline assembly in AICPU files.
Description check ✅ Passed The description directly explains the x86_64 compilation issue and the aarch64 guard/stub solution in the changed files.

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Code Review

This pull request introduces platform-specific preprocessor guards for aarch64 architectures in cache_ops.cpp and device_time.cpp, providing fallback implementations for non-aarch64 platforms. A review comment suggests improving the fallback for get_sys_cnt_aicpu() by returning device_time_now_ticks() instead of a constant 0 to avoid potential infinite loops or hangs in timeout polling logic.

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Comment on lines +19 to +21
#else
uint64_t get_sys_cnt_aicpu() { return 0; }
#endif

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medium

Returning a constant 0 in the x86 fallback stub can lead to infinite loops or hangs if any calling code uses get_sys_cnt_aicpu() for timeout polling (e.g., while (get_sys_cnt_aicpu() - start < timeout)). Since device_time_now_ticks() is already defined in aicpu/device_time.h and provides a proper monotonic clock fallback on non-aarch64 platforms, we should use it here to ensure robustness and prevent potential hangs during testing or simulation.

#else
uint64_t get_sys_cnt_aicpu() { return device_time_now_ticks(); }
#endif

Instead of returning 0 in the x86_64 fallback (which could cause
infinite loops in timeout polling code), use device_time_now_ticks()
which provides a proper monotonic clock based on std::chrono::steady_clock.

Addresses review feedback about potential hangs in code like:
  while (get_sys_cnt_aicpu() - start < timeout) { ... }

device_time_now_ticks() already handles the platform split correctly:
- aarch64: reads CNTVCT_EL0 hardware counter
- x86_64: returns nanoseconds from steady_clock
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2 participants