- Hyderabad
- in/vijay-kumar-b9a9bb271
Popular repositories Loading
-
RTL_DESIGN_MASTERY
RTL_DESIGN_MASTERY PublicIn these Repo i am gonna sharing my journey towards learning RTL design and synthesis
-
50_DAYS_OF_VERILOG
50_DAYS_OF_VERILOG PublicMy journey of building strong foundation in RTL design
Verilog 1
-
RISC_V_MASTERY
RISC_V_MASTERY PublicMy learning path of understanding of RISC_V with the help VSD System Design
-
4kB-SRAM-IP-Design-Verification
4kB-SRAM-IP-Design-Verification PublicThis repository documents my work completed under VSD as part of the AI-Assisted 4KB SRAM IP Design Internship. It covers the design, analysis, verification, and documentation of a 4KB SRAM IP usin…
-
Scalable-Duplicate-Detection-Engine
Scalable-Duplicate-Detection-Engine PublicParameterized RTL engine for duplicate detection using comparator-matrix architecture and duplicate analysis.
Verilog
-
PHYSICAL_VERIFICATION_TAPEOUT_READY_SKY130
PHYSICAL_VERIFICATION_TAPEOUT_READY_SKY130 PublicHands-on documentation of tapeout-ready physical verification using SKY130 PDK, Magic, Netgen, Xschem, ngspice, and OpenLANE.
If the problem persists, check the GitHub status page or contact support.