SystemRDL 2.0 language compiler front-end

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

C++ 17 Hardware abstraction layer generator from systemrdl

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Generate verilog register file from systemRDL description

A Xtext based SystemRDL editor with syntax highlighting and context sensitive help

HiSilicon ip camera SoCs SystemRDL registers description

VHDL generator from SystemRDL

Simulation and implementation flow for hardware description languages

SystemRDL language support for VS Code

HiSilicon SoC`s U-Boot initial register table parser into human readable format

Generate Rust code from SystemRDL for accessing control/status registers.

A SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.

Semantic compatibility analysis and configurable quality gates for SystemRDL specifications. Detects firmware-breaking register changes, produces CI reports and provides scalable exploration of large register maps.

An abstract language model of SystemRDL written in Python.

Generate BEAM (Erlang and Elixir) modules from a SystemRDL register model

SystemRDL lexer for Pygments syntax highlighting

APB Control interface for the ETH FLL