post-synthesis

Here are 3 public repositories matching this topic...

algosup / 2024-2025-project-4-web-fpga-team-6

A web FPGA simulator which takes as an input post-synthesis files of an FPGA design, and displays the components in an structured way. It allows to see the signal flow at custom speed and clock rate to analyse the impact of the clock frequency on the execution of a design.

simulator fpga webapp post-synthesis

Updated Mar 18, 2026
TypeScript

scale-lab / Pluto

Star

Pluto: A Benchmark for Evaluating Efficiency of LLM-generated Hardware Code

hardware ppa efficiency verilog llm post-synthesis

Updated Mar 22, 2026
Verilog

mannan-wadhwa / mealy-fsm-2s-complement

Star

Implements a Mealy FSM that computes the 2’s complement of a serial binary input, showcasing the full hardware design workflow from logic to gate-level simulation.

end-to-end verification verilog synthesis verilog-project timing-analysis rtl-design post-synthesis

Updated Jul 13, 2025
Verilog

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