clock-tree

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ieee-ceda-datc / RDF-2019

DATC RDF

routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree

Updated Jul 31, 2020
Verilog

Adaptation of the Zephyr CAN counter sample for the STM32 NUCLEO-C562RE with full CAN-FD support (1 Mbps nominal, 5 Mbps data), including the board overlay for the required FDCAN clock configuration (100 MHz kernel clock).

embedded stm32 device-tree zephyr rcc pll nucleo-board can-fd zephyr-rtos fdcan clock-tree stm32c5 clock-config stm32c562 nucleo-c562re

Updated Jul 1, 2026
C

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clock-tree

Here are 2 public repositories matching this topic...

ieee-ceda-datc / RDF-2019

gbdve / zephyr_can_counter

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