Vayu-143 / VLSI-Digital-Clock-with-Alarm Star 0 Code Issues Pull requests Industry-Oriented VLSI Digital Clock with Alarm Functionality implemented in Verilog HDL featuring Clock Divider, BCD Counters, Alarm Controller, RTL Design, Verification Testbench, GTKWave Simulation, and FPGA-Ready Architecture. fpga verification embedded-systems verilog alarm-clock systemverilog gtkwave digital-clock clock-divider rtl-design bcd-counter Updated Jun 18, 2026 Verilog