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colluca wants to merge 2 commits into from
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Bump common_cells to v2 #25

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35de259
Bump common_cells to v2
colluca May 16, 2026
46cb33a
Guard non-synthesizable constructs
colluca Jun 2, 2026
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2 changes: 1 addition & 1 deletion README.md
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Expand Up @@ -64,7 +64,7 @@ All IEEE 754-2008 status flags are supported, namely
### Dependencies

FPnew currently depends on the following:
- `lzc` and `rr_arb_tree` from the `common_cells` repository (https://github.com/pulp-platform/common_cells.git)
- `cc_lzc` and `cc_rr_arb_tree` from the `common_cells` repository (https://github.com/pulp-platform/common_cells.git)
- optional: Divider and square-root unit from the `fpu-div-sqrt-mvp` repository (https://github.com/pulp-platform/fpu_div_sqrt_mvp.git)

These two repositories are included in the source code directory as git submodules, use
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5 changes: 2 additions & 3 deletions src/fpnew_cast_multi.sv
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Expand Up @@ -275,9 +275,8 @@ module fpnew_cast_multi #(
logic [LZC_RESULT_WIDTH:0] renorm_shamt_sgn; // signed form for calculations

// Leading-zero counter is needed for renormalization
lzc #(
.WIDTH ( INT_MAN_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
cc_lzc #(
.Width ( INT_MAN_WIDTH )
) i_lzc (
.in_i ( encoded_mant ),
.cnt_o ( renorm_shamt ),
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5 changes: 2 additions & 3 deletions src/fpnew_fma.sv
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Expand Up @@ -503,9 +503,8 @@ module fpnew_fma #(
assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0];

// Leading zero counter for cancellations
lzc #(
.WIDTH ( LOWER_SUM_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
cc_lzc #(
.Width ( LOWER_SUM_WIDTH )
) i_lzc (
.in_i ( sum_lower ),
.cnt_o ( leading_zero_count ),
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5 changes: 2 additions & 3 deletions src/fpnew_fma_multi.sv
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Expand Up @@ -591,9 +591,8 @@ module fpnew_fma_multi #(
assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0];

// Leading zero counter for cancellations
lzc #(
.WIDTH ( LOWER_SUM_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
cc_lzc #(
.Width ( LOWER_SUM_WIDTH )
) i_lzc (
.in_i ( sum_lower ),
.cnt_o ( leading_zero_count ),
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6 changes: 3 additions & 3 deletions src/fpnew_opgroup_block.sv
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Expand Up @@ -227,14 +227,14 @@ module fpnew_opgroup_block #(
output_t arbiter_output;

// Round-Robin arbiter to decide which result to use
rr_arb_tree #(
cc_rr_arb_tree #(
.NumIn ( NUM_FORMATS ),
.DataType ( output_t ),
.data_t ( output_t ),
.AxiVldRdy ( 1'b1 )
) i_arbiter (
.clk_i,
.rst_ni,
.flush_i,
.clr_i ( flush_i ),
.rr_i ( '0 ),
.req_i ( fmt_out_valid ),
.gnt_o ( fmt_out_ready ),
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2 changes: 2 additions & 0 deletions src/fpnew_opgroup_multifmt_slice.sv
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Expand Up @@ -66,6 +66,7 @@ module fpnew_opgroup_multifmt_slice #(
output logic busy_o
);

`ifndef SYNTHESIS
if ((OpGroup == fpnew_pkg::DIVSQRT)) begin
if ((DivSqrtSel == fpnew_pkg::TH32) && !((FpFmtConfig[0] == 1) && (FpFmtConfig[1:NUM_FORMATS-1] == '0))) begin
$fatal(1, "T-Head-based DivSqrt unit supported only in FP32-only configurations. \
Expand Down Expand Up @@ -93,6 +94,7 @@ or on 16b inputs producing 32b outputs");
$fatal(1, "MXDOTP requires FP8 to be enabled as a source format. Please enable FP8 in MxFpFmtConfig.");
end
end
`endif

localparam int unsigned MAX_FP_WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig);
localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig);
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5 changes: 2 additions & 3 deletions src/fpnew_sdotp_multi.sv
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Expand Up @@ -1166,9 +1166,8 @@ module fpnew_sdotp_multi #(
assign sum_lower = {(~effective_subtraction_z && sum_carry_z), sum_z};

// Leading zero counter for cancellations
lzc #(
.WIDTH ( LZC_SUM_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
cc_lzc #(
.Width ( LZC_SUM_WIDTH )
) i_lzc (
.in_i ( sum_lower ),
.cnt_o ( leading_zero_count ),
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8 changes: 4 additions & 4 deletions src/fpnew_top.sv
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Expand Up @@ -168,15 +168,15 @@ module fpnew_top #(
output_t arbiter_output;

// Round-Robin arbiter to decide which result to use
rr_arb_tree #(
cc_rr_arb_tree #(
.NumIn ( NUM_OPGROUPS ),
.DataType ( output_t ),
.data_t ( output_t ),
.AxiVldRdy ( 1'b1 )
) i_arbiter (
.clk_i,
.rst_ni,
.flush_i,
.rr_i ( '0 ),
.clr_i ( flush_i ),
.rr_i ( '0 ),
.req_i ( opgrp_out_valid ),
.gnt_o ( opgrp_out_ready ),
.data_i ( opgrp_outputs ),
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2 changes: 1 addition & 1 deletion src/fpu_div_sqrt_mvp
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Submodule fpu_div_sqrt_mvp updated 2 files
+2 −2 hdl/norm_div_sqrt_mvp.sv
+4 −6 hdl/preprocess_mvp.sv
5 changes: 2 additions & 3 deletions src/mxdotp/fpnew_mxdotp_multi_modules.sv
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Expand Up @@ -814,9 +814,8 @@ module fpnew_mxdotp_normalizer
);

// Leading sign counter
lzc #(
.WIDTH ( LZC_SUM_WIDTH ),
.MODE ( 1 ) // MODE = 1 counts leading zeroes
cc_lzc #(
.Width ( LZC_SUM_WIDTH )
) i_lzc (
.in_i ( sum_magnitude ),
.cnt_o ( leading_zero_count ),
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