Skip to content
View jayjain2365's full-sized avatar

Block or report jayjain2365

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
jayjain2365/README.md

💫 Hii Jay Jain here!

About Me

Electronics Engineering student with strong interest in VLSI, RTL Design, and Digital System Design.
Currently focused on building practical projects in Verilog and SystemVerilog, including RISC processors, pipelined architectures, and digital design modules.

Areas of Interest

  • RTL Design
  • ASIC Verification
  • Digital Electronics
  • Computer Architecture
  • FPGA Design
  • RISC-V Architecture

Technical Skills

  • Verilog HDL
  • SystemVerilog
  • Digital Design
  • Computer Organization & Architecture
  • GTKWave
  • Vivado
  • ModelSim
  • Cadence Virtuoso
  • EDA playground
  • microcontrollers (Arduino, ESP8266, ESP32)

Current Projects

  • 8-bit RISC CPU
  • RISC-V Pipelined Processor
  • FSM based projects

Currently Learning

  • Advanced RTL Design
  • ASIC Verification Concepts
  • SystemVerilog Assertions
  • UVM Basics

Goal

To build strong expertise in RTL Design and Verification while developing industry-level VLSI projects.

🌐 Socials:

Instagram LinkedIn email HDLBits

💻 Tech Stack:

HDL & Verification

Verilog SystemVerilog UVM RTL Design ASIC Verification Digital Design RISC-V FPGA

EDA Tools

Vivado ModelSim GTKWave Cadence Virtuoso EDA Playground

Programming Languages

AssemblyScript Python JavaScript HTML5 CSS3 Arduino

📊 GitHub Stats:



Pinned Loading

  1. RISC-V-Pipelined-Processor-Verilog- RISC-V-Pipelined-Processor-Verilog- Public

    5-Stage RISC-V Pipelined Processor designed in Verilog HDL featuring Instruction Fetch, Decode, Execute, Memory Access, and Write-Back stages with RTL simulation and verification.

    Verilog

  2. 4bit-processor-verilog 4bit-processor-verilog Public

    4-bit Processor designed in Verilog HDL featuring Fetch, Decode, Execute and Write-Back stages with ALU operations, register file implementation, simulation, and FPGA synthesis using Xilinx Vivado.

    Verilog

  3. DecodeLabs-IoT-Internship DecodeLabs-IoT-Internship Public

    Collection of IoT and Embedded Systems projects developed during the DecodeLabs Internship using ESP32, sensors, cloud connectivity, and real-time monitoring applications.

    C++

  4. elevator_using_sv elevator_using_sv Public

    FSM-based Elevator Controller implemented in SystemVerilog with functional verification using Xilinx Vivado.

    SystemVerilog

  5. uart-transceiver-verilog uart-transceiver-verilog Public

    UART Transceiver (TX/RX) implemented in Verilog HDL using 8N1 protocol with Vivado simulation.

    Verilog