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fix(uno): drain stray UART RX bytes after Serial.begin()#44

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dim20:fix/stray-uart-rx-bytes
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fix(uno): drain stray UART RX bytes after Serial.begin()#44
dim20 wants to merge 1 commit into
henols:betafrom
dim20:fix/stray-uart-rx-bytes

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@dim20

@dim20 dim20 commented Jul 17, 2026

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Problem

After boot (or any rurp_set_communication_mode() call), the Uno's COBS decoder in loop() sometimes picks up a stray byte that doesn't form a valid frame. This triggers MSG_ERR_EMPTY_INPUT, which on the host side arrives before the real OK ack and causes the connection probe to fail.

The host sees:

Fix

Add a 100 ms settle delay after the initial UART RX flush in rurp_set_communication_mode(), then a second flush. This catches stray bytes that arrive after the first flush regardless of their origin.

Root cause note

The exact source of the stray byte has not been confirmed with a logic analyser. It is likely a late byte from the ATmega16U2 USB-serial bridge that lands after the initial flush, but could also be an electrical glitch on PD0 during the DDR transition. The settle delay + second flush is harmless either way.

Tested

Bench-tested on Uno R3 (ATmega16U2) with firmware 3.0.0b10 — the stale MSG_ERR_EMPTY_INPUT messages no longer appear.

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Code Review

This pull request adds a 100ms delay and a second serial port flush in src/boards/uno_rurp_shield.cpp to handle stray bytes from the USB-serial bridge during UART initialization. Feedback suggests that this double-flush pattern is redundant and introduces a race condition where legitimate host data could be discarded during the delay; it is recommended to use a single delay followed by a single flush instead.

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Comment thread src/boards/uno_rurp_shield.cpp Outdated
After boot (or any rurp_set_communication_mode() call), the Uno's COBS
decoder in loop() sometimes picks up a stray byte that doesn't form a
valid frame.  This triggers MSG_ERR_EMPTY_INPUT which, on the host
side, arrives before the real OK ack and causes the connection probe
to fail.

Replace the immediate post-init flush with a 100 ms settle delay
followed by a single flush.  This lets late-arriving stray bytes
(from the ATmega16U2 USB-serial bridge or an electrical glitch on
PD0) accumulate before we drain them, rather than flushing twice.

Bench-tested on Uno R3 (ATmega16U2) with firmware 3.0.0b10.
@dim20
dim20 force-pushed the fix/stray-uart-rx-bytes branch from 641a7ba to 81a7149 Compare July 17, 2026 11:04
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