aarch64: GICv2 driver and architectural timer subsystem - #6
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Signed-off-by: Graham MacDonald <grahamamacdonald@gmail.com>
Signed-off-by: Graham MacDonald <grahamamacdonald@gmail.com>
Signed-off-by: Graham MacDonald <grahamamacdonald@gmail.com>
req_buffer_va/req_buffer_pa held VirtRange/PhysRange values; name them req_buf_virtrange/req_buf_physrange like the rest of the file. Also drop an unused pub on mbox_virtrange.
Add port::irq with an RAII IrqGuard (mask IRQs on new, restore the previous state on drop; nestable; no-op until an arch registers its mask/restore hooks) and an interrupt-depth counter (enter_interrupt/ exit_interrupt/in_interrupt) so subsystems can either mask around locks shared with interrupt context or assert they are never used from it. aarch64 registers a DAIF-based implementation at early boot and brackets the trap handler with the depth counter. Other arches are unaffected: the guard is a no-op and in_interrupt is always false until they opt in.
The console Uart is now held as &'static dyn Uart rather than &mut: putb only needs a shared reference, and a shared reference lets the same Uart be aliased by the new direct-print path. Add iprint/iprintln in the tradition of Plan 9's iprint: mask IRQs, take only a best-effort bounded-spin interlock, and write polled bytes straight to the hardware, bypassing the console lock. This is the print for interrupt context, panic, and console/lock debugging; each arch registers a direct byte writer at console init. The console lock itself becomes thread-context-only, enforced with a debug assertion, so println no longer needs to mask IRQs around UART output. The aarch64 panic handler and trap handler switch to iprintln accordingly.
Add a GIC-400/GICv2 driver: distributor and CPU interface init from the devicetree (arm,gic-400, falling back to arm,cortex-a15-gic as used by qemu virt), ack/EOI from the trap handler, and per-INTID enable/disable using the general ISENABLER/ICENABLER indexing. An unhandled IRQ is disabled at the distributor before EOI, since EOI alone would let a still-asserted level-triggered source re-raise immediately. The timer subsystem uses caller-owned timers: each Timer lives in a static, the subsystem stores only &'static references in a small fixed table, and the interrupt handler neither allocates nor frees. One-shot and periodic timers share a TimerCallback trait fired in interrupt context; cancellation is a lazy active flag. The hardware is armed for the earliest active deadline, and re-arming (future CVAL, or disable when idle) is also what deasserts the level-triggered interrupt. Locks shared with the interrupt handler are taken under IrqGuard, and allocation in interrupt context is now a checked invariant in with_allocator rather than an unlucky-timing panic. Timer delivery goes through the GIC ack path only: the ISTATUS polling fallback and boot-time CNTP enable are gone, and arm_hardware is the sole owner of CNTP_CTL.ENABLE. Includes demo tickers in main.rs exercising the periodic, one-shot and cancellation paths.
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Adds a GIC-400/GICv2 driver — distributor and CPU interface init from the devicetree (
arm,gic-400, falling back toarm,cortex-a15-gicas used by qemu virt), ack/EOI from the trap handler, and per-INTID enable/disable using the general ISENABLER/ICENABLER indexing. An unhandled IRQ is disabled at the distributor before EOI, since EOI alone would let a still-asserted level-triggered source re-raise immediately.The timer subsystem uses caller-owned timers: each
Timerlives in a static, the subsystem stores only&'staticreferences in a small fixed table, and the interrupt handler neither allocates nor frees. One-shot and periodic timers share aTimerCallbacktrait fired in interrupt context; cancellation is a lazy active flag. The hardware is armed for the earliest active deadline, and re-arming (future CVAL, or disable when idle) is also what deasserts the level-triggered interrupt.Locks shared with the interrupt handler are taken under
IrqGuard, and allocation in interrupt context is now a checked invariant inwith_allocator. Timer delivery goes through the GIC ack path only: the ISTATUS polling fallback and boot-time CNTP enable are gone, andarm_hardwareis the sole owner of CNTP_CTL.ENABLE. Includes demo tickers in main.rs exercising the periodic, one-shot and cancellation paths.Stacked on #5; review the last commit.