[KMCompiler][TLE] Common IR triton35 - #974
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Co-authored-by: zhongsanming <sanming.zhong@compiler-dev.com>
* feat(test): add matmul_dsa_slice (#26) * feat(test): add matmul_dsa_slice * feat(test): use double buffer * docs(docs): add md file * [TileIRToHIVM] Lower scattered-pointer tile.copy via tt.load/tt.store (#35) A tile.copy whose source or destination is a scattered pointer (tensor<Nx!tt.ptr>) cannot be turned into a structured DMA in this pass, and previously produced an unresolved materialization cast that failed later in the pipeline. Rewrite such copies back into triton tt.load / tt.store so the access rejoins flir normal lowering path, where PtrAnalysis structures it downstream (reducing to a contiguous DMA when the indices are contiguous). Non-scattered copies (on-chip buffers, block pointers) keep their existing hivm.copy / memref.copy lowering unchanged. Co-authored-by: Your Name <you@example.com> --------- Co-authored-by: 103yiran <1039105206@qq.com> Co-authored-by: Shane <93116528+LeBlanc9@users.noreply.github.com> Co-authored-by: Your Name <you@example.com>
Co-authored-by: zhongsanming <sanming.zhong@compiler-dev.com>
对double buffer处理默认为编译器处理 算子处理会出现a loop-carried value of the outer task loop 同时EnableStrideAlign处理时会生成unrealized_conversion_cast 解决方案：算子不生成double buffer逻辑 将double buffer逻辑交给编译器处理 GraphSyncBlock问题： 如果算子控制workspace和CV 同步 需要使用_USE_CUSTOM_COMPILE_OPT，将bisheng编译器相关编译选项关闭
* test(test): add matmul subview * test(test): add no sync fa * test(test): add gpu pass fa * test(test): add fa_serial * test(test): add missing sync * fix(test): recover sub function * refactor(test): remove used variables * fix(third_party): add tile::MemorySpace::Global * fix(CMakeLists.txt): add no-dangling-assignment-gsl
* fix(test): fix L0C to UB error * fix(test): fix L0C to UB error * test(test): add fa 4func * test(test): add fa serial * test(test): add matmul_low_dim
* fix(test): fix cube use ub error * refactor(test): use tl.load
* fix(test): fix cube use ub error * refactor(test): use tl.load * fix(test): remove l1 alloc and copy, fix sync error
Co-authored-by: zhongsanming <zhongsanming@compiler-dev.com>
* fix(test): fix cube use ub error * refactor(test): use tl.load * fix(test): fix fa compile error * fix(test): fix rebase error
* update commit id of flir * remove docs * remove script folder * rename TileIR to CommonIR * revert unrelevant changes * revert changes unrelated to ascend * revert changes to backend testing tools * revert unrelated create_tanh ffi * revert compiler flags * remove HIVM dependency of tle * remove redundant header include directory * guard commonir c++ changes with __TLE_DSA__ * add commonir python comments and guard * change the license header for newly added source * run commonir success tests in ascend ci * move common ir unit test to it's own folder * add more python comment * remove envvar to replace ir * move common ir changes to tle/dsa * add more python comments * add comment to explain flir commit id changes --------- Co-authored-by: zhongsanming <zhongsanming@compiler-dev.com>
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相关SIG flagos-ai/community#95
引入一种新的Common IR作为TTIR的补充，CommonIR的主要功能是对算子层暴露更低层次的抽象，让算子层能解锁更多优化的机会。这个PR在triton 3.5 分支上完成了昇腾设备的POC工作，打通了从tle.dsa到Common IR到linalg IR到npubin的全流程。
现有flaggems全量op的精度测试结果：飞书文档
如果飞书文档没有权限请先使用以下链接：
summary
环境配置：
精度测试环境：
FlagGems: flaggems主线分支
FlagTree:
triton_v3.5 分支提交: flagtree 3.5
commonir 提交: common ir特性分支