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1. Statistical-Model-for-Power-Consumption-of-VLSI-Circuits-and-Effect-of-Quantized-Audio-Signal Statistical-Model-for-Power-Consumption-of-VLSI-Circuits-and-Effect-of-Quantized-Audio-Signal Public

   My Master's Thesis Project at IIT Kharagpur, (May'24 - June'25), [Place: IPCV Lab, E&ECE, IIT Kharagpur]

   MATLAB

2. Verilog_practice Verilog_practice Public

   This repository is dedicated to the practice of RTL design using Verilog HDL. It includes implementations of both combinational and sequential circuits, showcasing fundamental concepts and techniqu…

   Verilog 4

3. Asynchronous-FIFO Asynchronous-FIFO Public

   RTL to GDS implementation of Asynchronous FIFO Module

   Tcl 2

4. Adder-Architecture-Comparison-with-Gate-Level-Timing-Analysis Adder-Architecture-Comparison-with-Gate-Level-Timing-Analysis Public

   ASIC Implementation of N(N=32) bit Full Adder (RTL to GDS)

   Verilog