al-nusrati
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<!-- HEADER --> <div align="center"> <img src="https://capsule-render.vercel.app/api?type=waving&color=0E7490&height=120§ion=header&text=&animation=fadeIn" width="100%"/> <img src="https://readme-typing-svg.herokuapp.com?font=JetBrains+Mono&weight=700&size=42&duration=3000&pause=1500&color=0E7490¢er=true&vCenter=true&width=700&height=80&lines=JAWAD+AHMED" alt="Name" /> </div> <!-- IDENTITY --> <div align="center"> **Computer Engineering · NUST CEME · Rawalpindi, Pakistan** <img src="https://readme-typing-svg.herokuapp.com?font=JetBrains+Mono&weight=500&size=16&duration=2800&pause=1200&color=F59E0B¢er=true&vCenter=true&width=600&height=40&lines=RTL+Designer+%26+FPGA+Developer;Bare-Metal+Embedded+%26+TinyML+Engineer;Computer+Architecture+Explorer;Cloud+%26+Systems+Builder;Targeting+Google+%7C+NVIDIA+%7C+ARM" alt="Roles" /> <br/> [](https://linkedin.com/in/jawad-ahmed-102457276) [](https://github.com/al-nusrati) [](https://codeforces.com/profile/al_nusrati) <br/> > *I don't just write code — I build the hardware it runs on.* <img src="https://user-images.githubusercontent.com/74038190/212284100-561aa473-3905-4a80-b561-0d28506553ee.gif" width="700" alt="tech animation"/> </div> --- <!-- ABOUT --> ```yaml # jawad.yaml role : "CE Undergrad → targeting Google / NVIDIA" focus : ["Computer Architecture", "RTL Design", "Embedded ML", "Cloud Systems"] current : "3rd Year · 4th Semester" languages : ["C++", "SystemVerilog", "Python", "Java", "PIC18 Assembly"] tools : ["Vivado", "ESP-IDF", "Docker", "Azure", "TFLite", "CMake"] boards : ["Basys-3 (Artix-7)", "ESP32-S3", "PIC18F452"] competitive : "Codeforces: al_nusrati · Rating: B+" building_next : "FPGA neural accelerator + quantum architecture exploration" ``` --- <!-- FEATURED PROJECTS --> ## ⬡ Selected Projects > *Showing work that represents depth over breadth — hardware, systems, and AI at the intersection.* --- ### `[01]` — 5-Stage Pipelined RISC-V Processor **SystemVerilog · Vivado · Harvard Architecture** Full RV32I + RV32M 32-bit CPU designed from scratch. 5-stage pipeline `IF → ID → EX → MEM → WB` with inter-stage registers, a **Forwarding Unit** resolving RAW data hazards, and a **Hazard Detection Unit** for load-use stalls. Signed/unsigned arithmetic verified in GTKWave (`−7 × 5 = −35`, `−7 × −1 = 7`). [](https://github.com/al-nusrati/Single-Cycle-RV32I-with-Multi-Cycle-Multiplier) --- ### `[02]` — FPGA Design Portfolio · Basys-3 **Verilog · SystemVerilog · Artix-7** Multi-system top-level design on a single Artix-7 fabric: - **OLED Pipeline** — 96×64 real-time image renderer, 6144-pixel dual frame buffer via `$readmemh`, SPI at 6.25 MHz - **8-bit ALU** — demonstrates all three HDL abstraction levels in one module: gate-level structural (AND), dataflow (OR), behavioral procedural (XOR, ADD, SUB) - **Full-Alphabet 7-Seg** — 62-character display driver, 200 Hz multiplexed refresh, 10 ms hardware debouncer - 15+ additional systems: CipherX8, FSA, pipelined XOR, full adder, sequential counter — all synthesized and validated on-board []() --- ### `[03]` — Autonomous RC Car · On-Device ML Steering **ESP32-S3 · ESP-IDF v5.5 · TensorFlow Lite · MobileNetV2** Bare-metal TinyML car with no Linux, no OS overhead. Trained MobileNetV2-0.35 steering-regression on the Udacity self-driving dataset (128×128 input, INT8 quantized, 599KB) and deployed directly on ESP32-S3-WROOM-1. Complete ESP-IDF firmware integrating OV3660 camera, LEDC motor PWM, MPU-6050 IMU, and HC-SR04 ultrasonic sensors. **40–60ms real-time inference latency via FreeRTOS.** [](https://github.com/al-nusrati/RC_Autonomous_Car) --- ### `[04]` — Cloud Deadlock Detection System **C++ · Docker · Azure · Nginx · Flask** Distributed task scheduler with live deadlock avoidance. Implemented **Banker's Algorithm** with 4 concurrent worker threads and a dedicated deadlock-detector thread in C++. File-bridge IPC (`state.json` ↔ `input.json`) connects C++ backend to Flask/FastAPI dashboard. Containerised via Docker, reverse-proxied via Nginx, deployed on **Azure RHEL VM (Standard D2s v3)** with CMake build. [](https://github.com/al-nusrati/Distributed-Task-Scheduler-with-Deadlock-Detection) --- ### `[05]` — TinyLlama · Self-Hosted LLM REST API **Azure · Docker · Ollama · Nginx** Self-hosted TinyLlama 1.1B on Azure via Ollama inside Docker, served publicly through Nginx as a clean REST API (`/health`, `/api/generate`). Debugged SELinux `httpd_can_network_connect`, firewalld rules, and Docker containerd storage overflow — remapped to 15 GB data disk via symlink. --- ### `[06]` — LogicLink · EDA Digital Logic Simulator **Java 21 · JavaFX · Maven · jpackage · WiX** Professional-grade EDA tool with a **decoupled MVC simulation engine** performing real-time Boolean algebra independently of the UI. SVG-based schematic rendering via JavaFX `SVGPath` for infinitely scalable vector gates. Distributed as a **65MB self-contained Windows `.exe`** with bundled JRE — built via Maven Shade + jpackage + WiX Toolset. [](https://github.com/al-nusrati/LogicLink) --- ### `[07]` — HIVE · Console Music Player **C++ · SFML · Custom DLL · ConsoleUtils** Custom templated Doubly Linked List for O(1) track navigation; domain layer holds a direct `node<Track>*` pointer, eliminating index traversal entirely. Integrated SFML Audio for real-time MP3 streaming. Shipped **ConsoleUtils** — an open-source C++ static library using ANSI escape codes for coloured interactive terminal UIs (now used independently). [](https://github.com/al-nusrati/Simple-Music-Player.git) [](https://github.com/al-nusrati/ConsoleUtils) --- <!-- SKILLS --> ## ⬡ Technical Depth ``` Hardware & RTL ████████████████████░░ SystemVerilog · Verilog · FPGA · PCB Design Computer Architecture ███████████████████░░░ Pipelines · Hazard Units · Memory Hierarchies Embedded Systems ████████████████░░░░░░ ESP-IDF · FreeRTOS · PIC18 · Bare-Metal Firmware Cloud & DevOps ██████████████░░░░░░░░ Azure · Docker · Nginx · CMake · Git AI / ML on Edge █████████████░░░░░░░░░ TFLite · INT8 Quant · MobileNetV2 · Ollama Systems Programming ████████████████████░░ C++ · Multithreading · IPC · DSA · OS Concepts ``` --- <!-- STATS --> ## ⬡ GitHub Activity <div align="center"> <img height="160em" src="https://github-readme-stats.vercel.app/api?username=al-nusrati&show_icons=true&theme=tokyonight&hide_border=true&count_private=true&include_all_commits=true"/> <img height="160em" src="https://github-readme-stats.vercel.app/api/top-langs/?username=al-nusrati&layout=compact&theme=tokyonight&hide_border=true&langs_count=6"/> </div> <div align="center">  </div> --- <!-- CURRENT FOCUS --> ## ⬡ Currently <img src="https://readme-typing-svg.herokuapp.com?font=JetBrains+Mono&size=13&duration=2500&pause=1000&color=0E7490&width=500&height=28&lines=Quantum+gate+models+%26+error+correction...;FPGA+neural+network+acceleration...;RISC-V+memory+hierarchy+internals...;Publishing+on+LinkedIn+%26+Dev.to...;Competitive+programming+on+Codeforces..." alt="Currently doing" /> ``` → Exploring quantum computer architecture (gate models, error correction) → Building toward FPGA neural network acceleration → Deepening RISC-V pipeline design and memory system internals → Publishing technical content on LinkedIn: embedded AI · cloud · hardware → Competitive programming · Codeforces: al_nusrati ``` --- <!-- FOOTER --> <div align="center"> ``` ╔══════════════════════════════════════════════════════╗ ║ "The closer to silicon, the closer to truth." ║ ╚══════════════════════════════════════════════════════╝ ``` *Open to research collaborations, internships, and hard problems.* **[ [LinkedIn](https://linkedin.com/in/jawad-ahmed-102457276) · [GitHub](https://github.com/al-nusrati) · Rawalpindi, PK ]** <br/> <img src="https://capsule-render.vercel.app/api?type=waving&color=0E7490&height=100§ion=footer&animation=fadeIn" width="100%"/> </div>
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