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VRM21-Studios/README.md

Hi there, I'm Ryadh ๐Ÿ‘‹

Welcome to VRM21 Studios โ€” Versatile Reconfigurable Modules

Vision, Rรชve, Magie โœจ

I am an Electrical Engineering graduate specializing in Digital IC Design, RTL Engineering, and Hardware-Software Co-Design. I am passionate about bridging the gap between low-level hardware architecture and high-level software control.

๐Ÿ› ๏ธ Core Focus

  • Digital IC & RTL Design: Writing highly optimized, reusable Verilog for FPGAs.
  • Computer Architecture: Custom RV32I RISC-V cores and AXI4/AXI-Stream interfaces.
  • Hardware Acceleration: High-performance Audio DSP pipelines (QMF, FIR/IIR filters, Spatial Audio, Spectral Processing) and AI architectures, including Spiking Neural Networks (SNNs) and Systolic Arrays.
  • HW/SW Co-Design: Utilizing Xilinx Vivado, Vitis, and the Python PYNQ framework for seamless IP control across platforms like Zynq UltraScale+, Kria KV260, and KR260.

๐Ÿ“ˆ Highlighted Expertise

My capstone and independent research heavily involve Xilinx adaptive SoCs. I have architected the VRM Series SoCโ€”a system utilizing a custom RISC-V CPU to orchestrate complex DSP hardware accelerators.

True to its origins in Voix, Rythme, Musique, my pinned repositories feature reference RTL implementations of various audio DSP nodes. These modules are designed with maximum flexibility in mind, ready to be reconfigured for diverse applications.

๐ŸŒฑ Current Endeavors

  • Expanding my knowledge footprint into Data Science and Machine Learning to further complement custom hardware AI accelerators.
  • Preparing and structuring robust RTL architectures for academic research and manuscript publications.

๐Ÿ“ซ Reach me at: LinkedIn | Email | ORCID: 0009-0000-2759-2235

Pinned Loading

  1. 8x8-Systolic-Array-Module-FPGA 8x8-Systolic-Array-Module-FPGA Public

    An AXI-native 8x8 systolic array accelerator in Verilog. Features pure dataflow pipelining, Q-format fixed-point arithmetic, and hardware validation on the Kria KV260 FPGA.

    Verilog 1

  2. VRM21-Studios.github.io VRM21-Studios.github.io Public

    Personal digital workspace and portfolio landing page for Ryadh Al Ariz. Built with pure HTML/CSS and hosted on GitHub Pages.

    HTML

  3. FIR-Module-FPGA FIR-Module-FPGA Public

    A FIR filter for 16-bit stereo PCM audio DSP implemented on an FPGA with fixed-point representation.

    Verilog 2 1

  4. VRM21-CPU-RISC-V-Series VRM21-CPU-RISC-V-Series Public

    Under Construction

    Verilog