🧠 Single-Cycle RISC-V Processor (RV32I)

A clean and functional single-cycle RISC-V (RV32I) processor implemented in SystemVerilog, supporting arithmetic, memory, control flow, and CSR-based exception handling.

This project is intended for academic labs, processor design courses, and viva demonstrations.

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✨ Features

• RV32I base instruction set
• Single-cycle datapath
• Register file with asynchronous read
• ALU supporting arithmetic, logic, and shift operations
• Load / Store memory support
• Branch and Jump control (BEQ, BNE, JAL, JALR)
• CSR support (mstatus, mie, mtvec, mepc, mcause)
• Exception handling and mret
• Modular and readable SystemVerilog design
• Ready-to-run testbench with waveform generation

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🗂️ Project Structure

controller.sv
csr_register.sv
csr_mem
data_mem.sv
imm_gen.sv
inst_dec.sv
inst_mem.sv
instruction_memory
mux.sv
pc.sv
processor.sv
reg_files.sv
register_file
tb_processor.sv
alu.sv
README.md

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▶ How to Run (QuestaSim + GTKWave)

1️⃣ Open terminal & clone Repo

git clone https://github.com/Tehseen-Ajmal/RISC-V-SingleCycle.git

2️⃣ Move to project directory

cd /RISC-V-SingleCycle

4️⃣ Compile all SystemVerilog files

vlog -sv *.sv

5️⃣ Run simulation (command-line mode)

vsim -c tb_processor -voptargs=+acc -do "run -all; quit"

6️⃣ View waveforms using GTKWave

gtkwave processor.vcd

processor.vcd is generated automatically by the testbench.

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📥 Instruction Memory Format

Instructions are loaded using $readmemb.

Each line must contain one 32-bit binary instruction:

00000000010100000000000100010011
00000000101000000000001000010011

Loaded in testbench as:

$readmemb("instruction_memory", dut.imem_inst.mem);

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🧪 Testbench Details

• Generates clock and reset
• Loads instruction memory and register file
• Verifies load/store operations
• Prints PASS / FAIL messages
• Dumps waveform file (processor.vcd) for debugging

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📌 Design Notes

• Single-cycle implementation (no pipelining)
• Word-addressed instruction memory
• Byte-addressed data memory
• Clean PC priority: Exception → Branch/Jump → PC+4
• Designed for clarity and academic evaluation

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👨‍💻 Author

Tehseen Ajmal
Computer Engineering
RISC-V | Digital Design | SystemVerilog

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⭐ Final Note

This project is suitable for:

• Processor design labs
• Academic demonstrations and viva
• Learning RISC-V datapath and control logic

If you find this useful, consider starring the repository ⭐