Angehu/perf gate poc - #3
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Replace the tools/perf_regression_gate tree wholesale with the latest revision from PR #3 (angehu/perf-gate-poc, "hardening fixes"), then re-layer the runner/ops wiring needed to actually run on the NVIDIA RTX-6000 fleet: - Public Isaac Sim image override (fork cannot pull nvcr.io/nvidian/*), NGC_API_KEY env, bench_matrix output, full checkout for the matrix step. - World-writable jit-cache + artifact bind mounts (chmod 0777) and WARP/CUDA cache env/mounts to fix the wp.init() PermissionError that the lazy task loader masked as a spurious mdp AttributeError. - Rolling JIT cache key so the warm cache refills each run instead of freezing empty, plus an opt-in type=gha image layer cache (gha-cache-scope) for fleets where ECR cannot be resolved. - Trim triggers to the runnable push path (pull-request/<N> + protected branches + manual dispatch); pull_request/merge_group never get fleet runners. - Rename baseline branch angehu/perf-baselines -> perf-baselines.
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