Add missing Neon intrinsics#440
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These intrinsics are present in LLVM and GCC, but not documented on the ACLE. Add them to close the gap.
| | M | 21 February 2025 | 2024Q4 | | ||
| | N | 06 June 2025 | 2025Q2 | | ||
| | O | 15 May 2026 | 2026Q1 | | ||
| | P | 07 July 2026 | 2026Q2 | |
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We will not have releases anymore, so maybe we dont need to change this anymore
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| * Added support for FEAT_F16F32DOT | ||
| * Added support for FEAT_F16F32MM and FEAT_F16MM | ||
| * Added documentation for missing Neon intrinsics |
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Same with this. Maybe we should change this section to be only:
Changes since 2026Q1:
| | <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8" target="_blank">vmovq_n_p8</a>(poly8_t value)</code> | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `v7/A32/A64` | | ||
| | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16" target="_blank">vmov_n_p16</a>(poly16_t value)</code> | `value -> rn` | `DUP Vd.4H,rn` | `Vd.4H -> result` | `v7/A32/A64` | | ||
| | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16" target="_blank">vmovq_n_p16</a>(poly16_t value)</code> | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` | | ||
| | <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p64" target="_blank">vmov_n_p64</a>(poly64_t value)</code> | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `A32/A64` | |
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Is this correct ' INS Dd.D[0],xn`, it is different from the others vmovq with poly types.
| | <code>poly8x16_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p8" target="_blank">vmovq_n_p8</a>(poly8_t value)</code> | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `v7/A32/A64` | | ||
| | <code>poly16x4_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p16" target="_blank">vmov_n_p16</a>(poly16_t value)</code> | `value -> rn` | `DUP Vd.4H,rn` | `Vd.4H -> result` | `v7/A32/A64` | | ||
| | <code>poly16x8_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovq_n_p16" target="_blank">vmovq_n_p16</a>(poly16_t value)</code> | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` | | ||
| | <code>poly64x1_t <a href="https://developer.arm.com/architectures/instruction-sets/intrinsics/vmov_n_p64" target="_blank">vmov_n_p64</a>(poly64_t value)</code> | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `A32/A64` | |
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Should we change this to also report v7?
| poly8x16_t vmovq_n_p8(poly8_t value) value -> rn DUP Vd.16B,rn Vd.16B -> result v7/A32/A64 | ||
| poly16x4_t vmov_n_p16(poly16_t value) value -> rn DUP Vd.4H,rn Vd.4H -> result v7/A32/A64 | ||
| poly16x8_t vmovq_n_p16(poly16_t value) value -> rn DUP Vd.8H,rn Vd.8H -> result v7/A32/A64 | ||
| poly64x1_t vmov_n_p64(poly64_t value) value -> rn INS Dd.D[0],xn Vd.1D -> result A32/A64 |
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This looks strange too.
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These intrinsics are present in LLVM and GCC, but not documented on the ACLE.
Add them to close the gap.
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