From 8959aa40d654b172b7cc7e4d9d0f8825034d963c Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Thu, 28 May 2026 09:00:36 +0000
Subject: [PATCH 01/21] Support implementing ExtraBackendMethods and
 WriteBackendMethods independently

---
 src/lib.rs | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/lib.rs b/src/lib.rs
index 6ca2ef88ef2..50f10947c6a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -335,9 +335,7 @@ fn new_context<'gcc, 'tcx>(tcx: TyCtxt<'tcx>) -> Context<'gcc> {
 }
 
 impl ExtraBackendMethods for GccCodegenBackend {
-    fn supports_parallel(&self) -> bool {
-        false
-    }
+    type Module = GccContext;
 
     fn codegen_allocator(
         &self,
@@ -420,6 +418,10 @@ impl WriteBackendMethods for GccCodegenBackend {
     type ModuleBuffer = ModuleBuffer;
     type ThinData = ();
 
+    fn supports_parallel(&self) -> bool {
+        false
+    }
+
     fn target_machine_factory(
         &self,
         _sess: &Session,

From a291dd0c80afc20858f676ab535de1cd07298fbc Mon Sep 17 00:00:00 2001
From: Scott McMurray <scottmcm@users.noreply.github.com>
Date: Sat, 23 May 2026 16:28:57 -0700
Subject: [PATCH 02/21] Stop needing an alloca for `catch_unwind`

Turns out these were all making `OperandValue::Immediate`s already -- the intrinsic always returns a primitive scalar -- so pretty easy to handle.

While I was looking at it, I also "rustified" the intrinsic signature a bit: returning a `bool` and taking a generic pointee and `unsafe fn`s cleans up the call in `std` a bit without making the implementation in the backend any harder.
---
 src/intrinsic/mod.rs | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs
index f56cec6ce22..2aabbbd7628 100644
--- a/src/intrinsic/mod.rs
+++ b/src/intrinsic/mod.rs
@@ -1361,7 +1361,7 @@ fn try_intrinsic<'a, 'b, 'gcc, 'tcx>(
         bx.call(bx.type_void(), None, None, try_func, &[data], None, None);
         // Return 0 unconditionally from the intrinsic call;
         // we can never unwind.
-        OperandValue::Immediate(bx.const_i32(0)).store(bx, dest);
+        OperandValue::Immediate(bx.const_bool(false)).store(bx, dest);
     } else {
         if wants_msvc_seh(bx.sess()) {
             unimplemented!();
@@ -1418,7 +1418,7 @@ fn codegen_gnu_try<'gcc, 'tcx>(
         let current_block = bx.block;
 
         bx.switch_to_block(then);
-        bx.ret(bx.const_i32(0));
+        bx.ret(bx.const_bool(false));
 
         // Type indicator for the exception being thrown.
         //
@@ -1432,7 +1432,7 @@ fn codegen_gnu_try<'gcc, 'tcx>(
         let ptr = bx.cx.context.new_call(None, eh_pointer_builtin, &[zero]);
         let catch_ty = bx.type_func(&[bx.type_i8p(), bx.type_i8p()], bx.type_void());
         bx.call(catch_ty, None, None, catch_func, &[data, ptr], None, None);
-        bx.ret(bx.const_i32(1));
+        bx.ret(bx.const_bool(true));
 
         // NOTE: the blocks must be filled before adding the try/catch, otherwise gcc will not
         // generate a try/catch.
@@ -1465,7 +1465,7 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>(
     // Define the type up front for the signature of the rust_try function.
     let tcx = cx.tcx;
     let i8p = Ty::new_mut_ptr(tcx, tcx.types.i8);
-    // `unsafe fn(*mut i8) -> ()`
+    // `unsafe fn(*mut Data) -> ()`
     let try_fn_ty = Ty::new_fn_ptr(
         tcx,
         ty::Binder::dummy(tcx.mk_fn_sig_rust_abi(
@@ -1474,7 +1474,7 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>(
             rustc_hir::Safety::Unsafe,
         )),
     );
-    // `unsafe fn(*mut i8, *mut i8) -> ()`
+    // `unsafe fn(*mut Data, *mut i8) -> ()`
     let catch_fn_ty = Ty::new_fn_ptr(
         tcx,
         ty::Binder::dummy(tcx.mk_fn_sig_rust_abi(
@@ -1483,10 +1483,10 @@ fn get_rust_try_fn<'a, 'gcc, 'tcx>(
             rustc_hir::Safety::Unsafe,
         )),
     );
-    // `unsafe fn(unsafe fn(*mut i8) -> (), *mut i8, unsafe fn(*mut i8, *mut i8) -> ()) -> i32`
+    // `unsafe fn(unsafe fn(*mut Data) -> (), *mut Data, unsafe fn(*mut Data, *mut i8) -> ()) -> bool`
     let rust_fn_sig = ty::Binder::dummy(cx.tcx.mk_fn_sig_rust_abi(
         [try_fn_ty, i8p, catch_fn_ty],
-        tcx.types.i32,
+        tcx.types.bool,
         rustc_hir::Safety::Unsafe,
     ));
     let rust_try = gen_fn(cx, "__rust_try", rust_fn_sig, codegen);

From 418adda25171b737cc6f17381ea5b79afccf1dd3 Mon Sep 17 00:00:00 2001
From: Vadim Petrochenkov <vadim.petrochenkov@gmail.com>
Date: Fri, 21 Nov 2025 21:58:09 +0300
Subject: [PATCH 03/21] resolve: Partially convert `ambiguous_glob_imports`
 lint into a hard error

---
 build_system/src/test.rs | 2 --
 1 file changed, 2 deletions(-)

diff --git a/build_system/src/test.rs b/build_system/src/test.rs
index 3f02df83995..2475a3a6a71 100644
--- a/build_system/src/test.rs
+++ b/build_system/src/test.rs
@@ -886,8 +886,6 @@ fn valid_ui_error_pattern_test(file: &str) -> bool {
         "type-alias-impl-trait/auxiliary/cross_crate_ice.rs",
         "type-alias-impl-trait/auxiliary/cross_crate_ice2.rs",
         "macros/rfc-2011-nicer-assert-messages/auxiliary/common.rs",
-        "imports/ambiguous-1.rs",
-        "imports/ambiguous-4-extern.rs",
         "entry-point/auxiliary/bad_main_functions.rs",
     ]
     .iter()

From c3101c0fd0bcd503cd90c955501bd3f572134faf Mon Sep 17 00:00:00 2001
From: Alex Crichton <alex@alexcrichton.com>
Date: Fri, 29 May 2026 15:45:10 -0700
Subject: [PATCH 04/21] Use a `ArrayVec` in `CastTarget`

This commit switches a fixed-size list of `[Option<Reg>; 8]` to instead
holding `ArrayVec<Reg, 8>` in the `CastTarget` type used when
calculating ABIs. This is inspired by [discussion on Zulip][link] where
I'm hoping to in the near future extend the usage of this to possibly
beyond 8 elements for a new WebAssembly ABI taking advantage of
multi-value. For now though this mostly just switches to
array/slice-like idioms of accessors rather than dealing with
`Option<Reg>` as the unit.

[link]: https://rust-lang.zulipchat.com/#narrow/channel/131828-t-compiler/topic/Using.20.60ArgAbi.3A.3Amake_direct_deprecated.60/with/598607139
---
 src/abi.rs | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/abi.rs b/src/abi.rs
index 7239a5bcb04..fb243ff842c 100644
--- a/src/abi.rs
+++ b/src/abi.rs
@@ -46,7 +46,7 @@ impl GccType for CastTarget {
             )
         };
 
-        if self.prefix.iter().all(|x| x.is_none()) {
+        if self.prefix.is_empty() {
             // Simplify to a single unit when there is no prefix and size <= unit size
             if self.rest.total <= self.rest.unit.size {
                 return rest_gcc_unit;
@@ -62,7 +62,7 @@ impl GccType for CastTarget {
         let mut args: Vec<_> = self
             .prefix
             .iter()
-            .flat_map(|option_reg| option_reg.map(|reg| reg.gcc_type(cx)))
+            .map(|reg| reg.gcc_type(cx))
             .chain((0..rest_count).map(|_| rest_gcc_unit))
             .collect();
 

From d5db9be1cbe86099dd143629bfe2b3b63dccef96 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Wed, 27 May 2026 12:22:03 +0200
Subject: [PATCH 05/21] add `extern "tail"` calling convention

---
 src/abi.rs     | 29 ++++++++++++++++++++---------
 src/context.rs |  8 ++++----
 2 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/src/abi.rs b/src/abi.rs
index fb243ff842c..1b7bb8c9077 100644
--- a/src/abi.rs
+++ b/src/abi.rs
@@ -10,7 +10,7 @@ use rustc_middle::bug;
 use rustc_middle::ty::Ty;
 use rustc_middle::ty::layout::LayoutOf;
 #[cfg(feature = "master")]
-use rustc_session::config;
+use rustc_session::{Session, config};
 use rustc_target::callconv::{ArgAttributes, CastTarget, FnAbi, PassMode};
 #[cfg(feature = "master")]
 use rustc_target::spec::Arch;
@@ -230,32 +230,43 @@ impl<'gcc, 'tcx> FnAbiGccExt<'gcc, 'tcx> for FnAbi<'tcx, Ty<'tcx>> {
 
     #[cfg(feature = "master")]
     fn gcc_cconv(&self, cx: &CodegenCx<'gcc, 'tcx>) -> Option<FnAttribute<'gcc>> {
-        conv_to_fn_attribute(self.conv, &cx.tcx.sess.target.arch)
+        conv_to_fn_attribute(cx.sess(), self.conv)
     }
 }
 
 #[cfg(feature = "master")]
-pub fn conv_to_fn_attribute<'gcc>(conv: CanonAbi, arch: &Arch) -> Option<FnAttribute<'gcc>> {
+pub fn conv_to_fn_attribute<'gcc>(sess: &Session, conv: CanonAbi) -> Option<FnAttribute<'gcc>> {
     let attribute = match conv {
         CanonAbi::C | CanonAbi::Rust => return None,
-        // gcc/gccjit does not have anything for this.
-        CanonAbi::RustPreserveNone => return None,
+        CanonAbi::RustPreserveNone => {
+            // This calling convention is LLVM-specific and unspecified.
+            sess.dcx()
+                .fatal("gcc/gccjit backend does not support RustPreserveNone calling convention")
+        }
+        CanonAbi::RustTail => {
+            // This calling convention is LLVM-specific and unspecified.
+            sess.dcx().fatal("gcc/gccjit backend does not support RustTail calling convention")
+        }
         CanonAbi::RustCold => FnAttribute::Cold,
         // Functions with this calling convention can only be called from assembly, but it is
         // possible to declare an `extern "custom"` block, so the backend still needs a calling
         // convention for declaring foreign functions.
         CanonAbi::Custom => return None,
-        // gcc/gccjit does not have anything for Swift's calling convention.
-        CanonAbi::Swift => panic!("gcc/gccjit backend does not support Swift calling convention"),
+        CanonAbi::Swift => {
+            // gcc/gccjit does not have anything for Swift's calling convention.
+            sess.dcx().fatal("gcc/gccjit backend does not support Swift calling convention")
+        }
         CanonAbi::Arm(arm_call) => match arm_call {
             ArmCall::CCmseNonSecureCall => FnAttribute::ArmCmseNonsecureCall,
             ArmCall::CCmseNonSecureEntry => FnAttribute::ArmCmseNonsecureEntry,
             ArmCall::Aapcs => FnAttribute::ArmPcs("aapcs"),
         },
-        CanonAbi::GpuKernel => match arch {
+        CanonAbi::GpuKernel => match &sess.target.arch {
             &Arch::AmdGpu => FnAttribute::GcnAmdGpuHsaKernel,
             &Arch::Nvptx64 => FnAttribute::NvptxKernel,
-            arch => panic!("Arch {arch} does not support GpuKernel calling convention"),
+            arch => sess
+                .dcx()
+                .fatal(format!("Arch {arch} does not support GpuKernel calling convention")),
         },
         // FIXME(antoyo): check if those AVR attributes are mapped correctly.
         CanonAbi::Interrupt(interrupt_kind) => match interrupt_kind {
diff --git a/src/context.rs b/src/context.rs
index ed313859aea..ea71546ea1c 100644
--- a/src/context.rs
+++ b/src/context.rs
@@ -486,10 +486,10 @@ impl<'gcc, 'tcx> MiscCodegenMethods<'tcx> for CodegenCx<'gcc, 'tcx> {
     fn declare_c_main(&self, fn_type: Self::Type) -> Option<Self::Function> {
         let entry_name = self.sess().target.entry_name.as_ref();
         if !self.functions.borrow().contains_key(entry_name) {
-            #[cfg(feature = "master")]
-            let conv = conv_to_fn_attribute(self.sess().target.entry_abi, &self.sess().target.arch);
-            #[cfg(not(feature = "master"))]
-            let conv = None;
+            let conv = cfg_select! {
+                feature = "master" => conv_to_fn_attribute(self.sess(), self.sess().target.entry_abi),
+                _ => None,
+            };
             Some(self.declare_entry_fn(entry_name, fn_type, conv))
         } else {
             // If the symbol already exists, it is an error: for example, the user wrote

From 774e911f18265d841d82d1445261c801c6671047 Mon Sep 17 00:00:00 2001
From: bjorn3 <17426603+bjorn3@users.noreply.github.com>
Date: Wed, 3 Jun 2026 15:01:07 +0000
Subject: [PATCH 06/21] Use WorkProductMap instead of FxIndexMap

This is an UnordMap internally. Iteration order for the work product map
should not matter aside from the place it is serialized where sorting by
WorkProductId is sufficient.
---
 src/lib.rs | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/lib.rs b/src/lib.rs
index 9669f401662..850b67c7b25 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -89,11 +89,10 @@ use rustc_codegen_ssa::base::codegen_crate;
 use rustc_codegen_ssa::target_features::cfg_target_feature;
 use rustc_codegen_ssa::traits::{CodegenBackend, ExtraBackendMethods, WriteBackendMethods};
 use rustc_codegen_ssa::{CompiledModule, CompiledModules, CrateInfo, ModuleCodegen, TargetConfig};
-use rustc_data_structures::fx::FxIndexMap;
 use rustc_data_structures::profiling::SelfProfilerRef;
 use rustc_data_structures::sync::IntoDynSyncSend;
 use rustc_errors::{DiagCtxt, DiagCtxtHandle};
-use rustc_middle::dep_graph::{WorkProduct, WorkProductId};
+use rustc_middle::dep_graph::{WorkProduct, WorkProductMap};
 use rustc_middle::ty::TyCtxt;
 use rustc_middle::util::Providers;
 use rustc_session::Session;
@@ -301,7 +300,7 @@ impl CodegenBackend for GccCodegenBackend {
         sess: &Session,
         _outputs: &OutputFilenames,
         crate_info: &CrateInfo,
-    ) -> (CompiledModules, FxIndexMap<WorkProductId, WorkProduct>) {
+    ) -> (CompiledModules, WorkProductMap) {
         ongoing_codegen
             .downcast::<rustc_codegen_ssa::back::write::OngoingCodegen<GccCodegenBackend>>()
             .expect("Expected GccCodegenBackend's OngoingCodegen, found Box<Any>")

From 5fb3b38f6a8096cd786122078b01866d56928153 Mon Sep 17 00:00:00 2001
From: Scott Mabin <scott@mabez.dev>
Date: Fri, 3 Oct 2025 16:50:06 +0100
Subject: [PATCH 07/21] asm! support for the Xtensa architecture

Co-authored-by: Taiki Endo <te316e89@gmail.com>
Co-authored-by: Kerry Jones <kerry@iodrive.co.za>
---
 src/asm.rs | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/asm.rs b/src/asm.rs
index 5bb65365ad6..e4b75dc462b 100644
--- a/src/asm.rs
+++ b/src/asm.rs
@@ -751,6 +751,11 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
             | X86InlineAsmRegClass::mmx_reg
             | X86InlineAsmRegClass::tmm_reg,
         ) => unreachable!("clobber-only"),
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => "r",
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => "f",
+        InlineAsmRegClass::Xtensa(
+            XtensaInlineAsmRegClass::sreg | XtensaInlineAsmRegClass::breg,
+        ) => unreachable!("clobber-only"),
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("GCC backend does not support SPIR-V")
         }
@@ -872,6 +877,11 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("GCC backend does not support SPIR-V")
         }
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::reg) => cx.type_i32(),
+        InlineAsmRegClass::Xtensa(XtensaInlineAsmRegClass::freg) => cx.type_f32(),
+        InlineAsmRegClass::Xtensa(
+            XtensaInlineAsmRegClass::sreg | XtensaInlineAsmRegClass::breg,
+        ) => unreachable!("clobber-only"),
         InlineAsmRegClass::Err => unreachable!(),
     }
 }
@@ -1070,6 +1080,7 @@ fn modifier_to_gcc(
         InlineAsmRegClass::SpirV(SpirVInlineAsmRegClass::reg) => {
             bug!("LLVM backend does not support SPIR-V")
         }
+        InlineAsmRegClass::Xtensa(_) => None,
         InlineAsmRegClass::Err => unreachable!(),
     }
 }

From 92029523af40d33b933aab1b08fbfbab01400277 Mon Sep 17 00:00:00 2001
From: Flakebi <flakebi@t-online.de>
Date: Wed, 3 Jun 2026 09:51:47 +0200
Subject: [PATCH 08/21] Add inline asm support for amdgpu
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Add support for inline assembly for the amdgpu backend (the
amdgcn-amd-amdhsa target).
Add register classes for `vgpr` (vector general purpose register) and
`sgpr` (scalar general purpose register).
The LLVM backend supports two more classes, `reg`, which is either VGPR
or SGPR, up to the compiler to decide. As instructions often rely on a
register being either a VGPR or SGPR for the assembly to be valid, reg
doesn’t seem that useful (I struggled to write correct tests for it), so
I didn’t end up adding it.
The fourth register class is AGPRs, which only exist on some hardware
versions (not the consumer ones) and they have restricted ways to write
and read from them, which makes it hard to write a Rust variable into
them. They could be used inside assembly blocks, but I didn’t add them
as Rust register class.

There are a few change affecting general inline assembly code, that is
`InlineAsmReg::name()` now returns a `Cow` instead of a `&'static str`.
Because amdgpu has many registers, 256 VGPRs plus combinations of 2 or 4
VGPRs, and I didn’t want to list hundreds of static strings, the amdgpu
reg stores the register number(s) and a non-static String is generated
at runtime for the register name.
Similar for register classes and supported_types.

Vectors of 64-bit types are supported by the LLVM backend, but omitted
here to make the code simpler. There is currently no systematic support
in LLVM of which vectors of 64-bit types are supported. Also, they are
likely seldomly unused, vectors of 16- and 32-bit types are important.
---
 src/asm.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/asm.rs b/src/asm.rs
index e4b75dc462b..53074e313f9 100644
--- a/src/asm.rs
+++ b/src/asm.rs
@@ -677,6 +677,8 @@ fn reg_class_to_gcc(reg_class: InlineAsmRegClass) -> &'static str {
         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
             unreachable!("clobber-only")
         }
+        InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Sgpr(_)) => "Sg",
+        InlineAsmRegClass::Amdgpu(AmdgpuInlineAsmRegClass::Vgpr(_)) => "v",
         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => "r",
         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg_low16)
@@ -785,6 +787,7 @@ fn dummy_output_type<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, reg: InlineAsmRegCl
         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
             unreachable!("clobber-only")
         }
+        InlineAsmRegClass::Amdgpu(_) => cx.type_i32(),
         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => cx.type_i32(),
         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => cx.type_f32(),
@@ -993,6 +996,7 @@ fn modifier_to_gcc(
         InlineAsmRegClass::AArch64(AArch64InlineAsmRegClass::preg) => {
             unreachable!("clobber-only")
         }
+        InlineAsmRegClass::Amdgpu(_) => None,
         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::reg) => None,
         InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg)
         | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::sreg_low16) => None,

From ef638de1a5f1c9caf632aa6deffbc22772c2cd42 Mon Sep 17 00:00:00 2001
From: Camille Gillot <gillot.camille@gmail.com>
Date: Wed, 10 Jun 2026 15:11:57 +0000
Subject: [PATCH 09/21] Move create_scope_map to rustc_codegen_ssa.

---
 src/debuginfo.rs | 151 ++++-------------------------------------------
 src/lib.rs       |   1 -
 2 files changed, 12 insertions(+), 140 deletions(-)

diff --git a/src/debuginfo.rs b/src/debuginfo.rs
index cf938a3988c..8907d8a42b3 100644
--- a/src/debuginfo.rs
+++ b/src/debuginfo.rs
@@ -3,13 +3,9 @@ use std::sync::Arc;
 
 use gccjit::{Function, Location, RValue};
 use rustc_abi::Size;
-use rustc_codegen_ssa::mir::debuginfo::{DebugScope, FunctionDebugContext, VariableKind};
+use rustc_codegen_ssa::mir::debuginfo::VariableKind;
 use rustc_codegen_ssa::traits::{DebugInfoBuilderMethods, DebugInfoCodegenMethods};
-use rustc_index::bit_set::DenseBitSet;
-use rustc_index::{Idx, IndexVec};
-use rustc_middle::mir::{self, Body, SourceScope};
 use rustc_middle::ty::{ExistentialTraitRef, Instance, Ty};
-use rustc_session::config::DebugInfo;
 use rustc_span::{BytePos, Pos, SourceFile, SourceFileAndLine, Span, Symbol};
 use rustc_target::callconv::FnAbi;
 
@@ -65,115 +61,6 @@ impl<'a, 'gcc, 'tcx> DebugInfoBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
     }
 }
 
-/// Generate the `debug_context` in an MIR Body.
-/// # Source of Origin
-/// Copied from `create_scope_map.rs` of rustc_codegen_llvm
-fn compute_mir_scopes<'gcc, 'tcx>(
-    cx: &CodegenCx<'gcc, 'tcx>,
-    instance: Instance<'tcx>,
-    mir: &Body<'tcx>,
-    debug_context: &mut FunctionDebugContext<'tcx, (), Location<'gcc>>,
-) {
-    // Find all scopes with variables defined in them.
-    let variables = if cx.sess().opts.debuginfo == DebugInfo::Full {
-        let mut vars = DenseBitSet::new_empty(mir.source_scopes.len());
-        // FIXME(eddyb) take into account that arguments always have debuginfo,
-        // irrespective of their name (assuming full debuginfo is enabled).
-        // NOTE(eddyb) actually, on second thought, those are always in the
-        // function scope, which always exists.
-        for var_debug_info in &mir.var_debug_info {
-            vars.insert(var_debug_info.source_info.scope);
-        }
-        Some(vars)
-    } else {
-        // Nothing to emit, of course.
-        None
-    };
-    let mut instantiated = DenseBitSet::new_empty(mir.source_scopes.len());
-    // Instantiate all scopes.
-    for idx in 0..mir.source_scopes.len() {
-        let scope = SourceScope::new(idx);
-        make_mir_scope(cx, instance, mir, &variables, debug_context, &mut instantiated, scope);
-    }
-    assert!(instantiated.count() == mir.source_scopes.len());
-}
-
-/// Update the `debug_context`, adding new scope to it,
-/// if it's not added as is denoted in `instantiated`.
-///
-/// # Source of Origin
-/// Copied from `create_scope_map.rs` of rustc_codegen_llvm
-/// FIXME(tempdragon/?): Add Scope Support Here.
-fn make_mir_scope<'gcc, 'tcx>(
-    cx: &CodegenCx<'gcc, 'tcx>,
-    _instance: Instance<'tcx>,
-    mir: &Body<'tcx>,
-    variables: &Option<DenseBitSet<SourceScope>>,
-    debug_context: &mut FunctionDebugContext<'tcx, (), Location<'gcc>>,
-    instantiated: &mut DenseBitSet<SourceScope>,
-    scope: SourceScope,
-) {
-    if instantiated.contains(scope) {
-        return;
-    }
-
-    let scope_data = &mir.source_scopes[scope];
-    let parent_scope = if let Some(parent) = scope_data.parent_scope {
-        make_mir_scope(cx, _instance, mir, variables, debug_context, instantiated, parent);
-        debug_context.scopes[parent]
-    } else {
-        // The root is the function itself.
-        let file = cx.sess().source_map().lookup_source_file(mir.span.lo());
-        debug_context.scopes[scope] = DebugScope {
-            file_start_pos: file.start_pos,
-            file_end_pos: file.end_position(),
-            ..debug_context.scopes[scope]
-        };
-        instantiated.insert(scope);
-        return;
-    };
-
-    if let Some(ref vars) = *variables
-        && !vars.contains(scope)
-        && scope_data.inlined.is_none()
-    {
-        // Do not create a DIScope if there are no variables defined in this
-        // MIR `SourceScope`, and it's not `inlined`, to avoid debuginfo bloat.
-        debug_context.scopes[scope] = parent_scope;
-        instantiated.insert(scope);
-        return;
-    }
-
-    let loc = cx.lookup_debug_loc(scope_data.span.lo());
-
-    // FIXME(tempdragon): Add the scope related code here if the scope is supported.
-    let dbg_scope = ();
-
-    let inlined_at = scope_data.inlined.map(|(_, callsite_span)| {
-        // FIXME(eddyb) this doesn't account for the macro-related
-        // `Span` fixups that `rustc_codegen_ssa::mir::debuginfo` does.
-
-        // FIXME(tempdragon): Add scope support and then revert to cg_llvm version of this closure
-        // NOTE: These variables passed () here.
-        // Changed to comply to clippy.
-
-        /* let callsite_scope =  */
-        parent_scope.adjust_dbg_scope_for_span(cx, callsite_span);
-        cx.dbg_loc(/* callsite_scope */ (), parent_scope.inlined_at, callsite_span)
-    });
-    let p_inlined_at = parent_scope.inlined_at;
-    // FIXME(tempdragon): dbg_scope: Add support for scope extension here.
-    inlined_at.or(p_inlined_at);
-
-    debug_context.scopes[scope] = DebugScope {
-        dbg_scope,
-        inlined_at,
-        file_start_pos: loc.file.start_pos,
-        file_end_pos: loc.file.end_position(),
-    };
-    instantiated.insert(scope);
-}
-
 /// A source code location used to generate debug information.
 // FIXME(eddyb) rename this to better indicate it's a duplicate of
 // `rustc_span::Loc` rather than `DILocation`, perhaps by making
@@ -228,33 +115,19 @@ impl<'gcc, 'tcx> DebugInfoCodegenMethods<'tcx> for CodegenCx<'gcc, 'tcx> {
         // FIXME(antoyo)
     }
 
-    fn create_function_debug_context(
+    fn dbg_create_lexical_block(
         &self,
-        instance: Instance<'tcx>,
-        fn_abi: &FnAbi<'tcx, Ty<'tcx>>,
-        llfn: Function<'gcc>,
-        mir: &mir::Body<'tcx>,
-    ) -> Option<FunctionDebugContext<'tcx, Self::DIScope, Self::DILocation>> {
-        if self.sess().opts.debuginfo == DebugInfo::None {
-            return None;
-        }
-
-        // Initialize fn debug context (including scopes).
-        let empty_scope = DebugScope {
-            dbg_scope: self.dbg_scope_fn(instance, fn_abi, Some(llfn)),
-            inlined_at: None,
-            file_start_pos: BytePos(0),
-            file_end_pos: BytePos(0),
-        };
-        let mut fn_debug_context = FunctionDebugContext {
-            scopes: IndexVec::from_elem(empty_scope, mir.source_scopes.as_slice()),
-            inlined_function_scopes: Default::default(),
-        };
-
-        // Fill in all the scopes, with the information from the MIR body.
-        compute_mir_scopes(self, instance, mir, &mut fn_debug_context);
+        _pos: BytePos,
+        _parent_scope: Self::DIScope,
+    ) -> Self::DIScope {
+    }
 
-        Some(fn_debug_context)
+    fn dbg_location_clone_with_discriminator(
+        &self,
+        loc: Self::DILocation,
+        _discriminator: u32,
+    ) -> Option<Self::DILocation> {
+        Some(loc)
     }
 
     fn extend_scope_to_file(
diff --git a/src/lib.rs b/src/lib.rs
index 850b67c7b25..4cc4a2d258d 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -30,7 +30,6 @@ extern crate rustc_data_structures;
 extern crate rustc_errors;
 extern crate rustc_fs_util;
 extern crate rustc_hir;
-extern crate rustc_index;
 #[cfg(feature = "master")]
 extern crate rustc_interface;
 extern crate rustc_log;

From 9b4d3208277dd5a6514901f4eb315cddcd4496e1 Mon Sep 17 00:00:00 2001
From: Folkert de Vries <folkert@folkertdev.nl>
Date: Mon, 8 Jun 2026 21:44:31 +0200
Subject: [PATCH 10/21] remove LLVM `va_end` calls

The operation is a no-op, so we skip it.
---
 src/intrinsic/mod.rs | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs
index 728cd90cf63..a12116d5b9d 100644
--- a/src/intrinsic/mod.rs
+++ b/src/intrinsic/mod.rs
@@ -705,10 +705,6 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc
         unimplemented!();
     }
 
-    fn va_end(&mut self, _va_list: RValue<'gcc>) {
-        // FIXME(antoyo): implement.
-    }
-
     fn retag_reg(&mut self, _ptr: Self::Value, _info: &RetagInfo<Self::Value>) -> Self::Value {
         unimplemented!()
     }

From 9ff44af040e6605fe1ee20275abe33998dea9d1c Mon Sep 17 00:00:00 2001
From: David Wood <david.wood2@arm.com>
Date: Mon, 22 Jun 2026 14:35:51 +0000
Subject: [PATCH 11/21] codegen_ssa: multiply scalable vec size by `vscale`

When emitting a `memcpy` for a scalable vector, the size computed by
rustc (`num_vectors * element_count * element_ty`), since
rust-lang/rust#157915, needs to be multiplied by `vscale`.
---
 src/builder.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/builder.rs b/src/builder.rs
index 33f0f6fc2f8..8ae4dedff8f 100644
--- a/src/builder.rs
+++ b/src/builder.rs
@@ -1459,6 +1459,10 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> {
         );
     }
 
+    fn vscale(&mut self, _: Self::Type) -> Self::Value {
+        unimplemented!("`rustc_codegen_gcc` doesn't support scalable vectors yet")
+    }
+
     fn select(
         &mut self,
         cond: RValue<'gcc>,

From 515a89c86addc7ce2a4291e1910b4a9708ff4bc0 Mon Sep 17 00:00:00 2001
From: Scott McMurray <scottmcm@users.noreply.github.com>
Date: Sat, 23 May 2026 15:27:28 -0700
Subject: [PATCH 12/21] cg_LLVM: Stop needing an alloca for volatile loads

And while I'm here, improve the tests to check that the unaligned ones are actually unaligned, since `unaligned_volatile_load::<u8>` doesn't actually test anything.
---
 src/builder.rs       | 3 ++-
 src/intrinsic/mod.rs | 7 ++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/builder.rs b/src/builder.rs
index 8ae4dedff8f..6cbc0054cc0 100644
--- a/src/builder.rs
+++ b/src/builder.rs
@@ -993,7 +993,8 @@ impl<'a, 'gcc, 'tcx> BuilderMethods<'a, 'tcx> for Builder<'a, 'gcc, 'tcx> {
         loaded_value.to_rvalue()
     }
 
-    fn volatile_load(&mut self, ty: Type<'gcc>, ptr: RValue<'gcc>) -> RValue<'gcc> {
+    fn volatile_load(&mut self, ty: Type<'gcc>, ptr: RValue<'gcc>, _: Align) -> RValue<'gcc> {
+        // FIXME(antoyo): set alignment.
         let ptr = self.context.new_cast(self.location, ptr, ty.make_volatile().make_pointer());
         // (FractalFir): We insert a local here, to ensure this volatile load can't move across
         // blocks.
diff --git a/src/intrinsic/mod.rs b/src/intrinsic/mod.rs
index a12116d5b9d..78a4c7e88c8 100644
--- a/src/intrinsic/mod.rs
+++ b/src/intrinsic/mod.rs
@@ -5,7 +5,7 @@ mod simd;
 use std::iter;
 
 use gccjit::{ComparisonOp, Function, FunctionType, RValue, ToRValue, Type, UnaryOp};
-use rustc_abi::{BackendRepr, HasDataLayout, WrappingRange};
+use rustc_abi::{Align, BackendRepr, HasDataLayout, WrappingRange};
 use rustc_codegen_ssa::base::wants_msvc_seh;
 use rustc_codegen_ssa::common::IntPredicate;
 use rustc_codegen_ssa::errors::InvalidMonomorphization;
@@ -368,8 +368,9 @@ impl<'a, 'gcc, 'tcx> IntrinsicCallBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tc
 
             sym::volatile_load | sym::unaligned_volatile_load => {
                 let ptr = args[0].immediate();
-                let load = self.volatile_load(result.layout.gcc_type(self), ptr);
-                // FIXME(antoyo): set alignment.
+                let abi_align = result_layout.align.abi;
+                let ptr_align = if name == sym::volatile_load { abi_align } else { Align::ONE };
+                let load = self.volatile_load(result.layout.gcc_type(self), ptr, ptr_align);
                 if let BackendRepr::Scalar(scalar) = result.layout.backend_repr {
                     self.to_immediate_scalar(load, scalar)
                 } else {

From 3d3ea2f2131c40f3772eedc0706db5ea8fa14367 Mon Sep 17 00:00:00 2001
From: Philipp Krones <hello@philkrones.com>
Date: Thu, 25 Jun 2026 18:50:36 +0200
Subject: [PATCH 13/21] cg_gcc: Fix Clippy lint fallout

---
 src/common.rs | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/src/common.rs b/src/common.rs
index dd0064d34bc..b9b6e51d3b8 100644
--- a/src/common.rs
+++ b/src/common.rs
@@ -58,13 +58,19 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
     // or is it using a more efficient representation?
     match bytes.len() % 8 {
         0 => {
+            debug_assert_eq!(
+                bytes.len() % 8,
+                0,
+                "bytes length is not a multiple of 8, so bytes.as_chunks will have a remainder"
+            );
             let context = &cx.context;
             let byte_type = context.new_type::<u64>();
             let typ = new_array_type(context, None, byte_type, bytes.len() as u64 / 8);
             let elements: Vec<_> = bytes
-                .chunks_exact(8)
-                .map(|arr| {
-                    let arr: [u8; 8] = arr.try_into().unwrap();
+                .as_chunks::<8>()
+                .0
+                .iter()
+                .map(|&arr| {
                     context.new_rvalue_from_long(
                         byte_type,
                         // Since we are representing arbitrary byte runs as integers, we need to follow the target
@@ -79,13 +85,19 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
             context.new_array_constructor(None, typ, &elements)
         }
         4 => {
+            debug_assert_eq!(
+                bytes.len() % 4,
+                0,
+                "bytes length is not a multiple of 4, so bytes.as_chunks will have a remainder"
+            );
             let context = &cx.context;
             let byte_type = context.new_type::<u32>();
             let typ = new_array_type(context, None, byte_type, bytes.len() as u64 / 4);
             let elements: Vec<_> = bytes
-                .chunks_exact(4)
-                .map(|arr| {
-                    let arr: [u8; 4] = arr.try_into().unwrap();
+                .as_chunks::<4>()
+                .0
+                .iter()
+                .map(|&arr| {
                     context.new_rvalue_from_int(
                         byte_type,
                         match cx.sess().target.options.endian {

From cf22ea918d719b235df739e978873c7e6c702715 Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 11:11:08 -0400
Subject: [PATCH 14/21] Update to nightly-2026-06-28

---
 rust-toolchain | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rust-toolchain b/rust-toolchain
index 7860423093b..ee95f8e6e1c 100644
--- a/rust-toolchain
+++ b/rust-toolchain
@@ -1,3 +1,3 @@
 [toolchain]
-channel = "nightly-2026-05-28"
+channel = "nightly-2026-06-28"
 components = ["rust-src", "rustc-dev", "llvm-tools-preview"]

From 3120a7a05b23f01937614e486753157d33b18d45 Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 11:11:22 -0400
Subject: [PATCH 15/21] Remove useless stdarch patch

---
 ...1-Add-stdarch-Cargo.toml-for-testing.patch | 39 -------------------
 1 file changed, 39 deletions(-)
 delete mode 100644 patches/0001-Add-stdarch-Cargo.toml-for-testing.patch

diff --git a/patches/0001-Add-stdarch-Cargo.toml-for-testing.patch b/patches/0001-Add-stdarch-Cargo.toml-for-testing.patch
deleted file mode 100644
index 3a8c37a8b8d..00000000000
--- a/patches/0001-Add-stdarch-Cargo.toml-for-testing.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 190e26c9274b3c93a9ee3516b395590e6bd9213b Mon Sep 17 00:00:00 2001
-From: None <none@example.com>
-Date: Sun, 3 Aug 2025 19:54:56 -0400
-Subject: [PATCH] Patch 0001-Add-stdarch-Cargo.toml-for-testing.patch
-
----
- library/stdarch/Cargo.toml | 20 ++++++++++++++++++++
- 1 file changed, 20 insertions(+)
- create mode 100644 library/stdarch/Cargo.toml
-
-diff --git a/library/stdarch/Cargo.toml b/library/stdarch/Cargo.toml
-new file mode 100644
-index 0000000..bd6725c
---- /dev/null
-+++ b/library/stdarch/Cargo.toml
-@@ -0,0 +1,20 @@
-+[workspace]
-+resolver = "1"
-+members = [
-+  "crates/*",
-+  #"examples/"
-+]
-+exclude = [
-+  "crates/wasm-assert-instr-tests",
-+  "rust_programs",
-+]
-+
-+[profile.release]
-+debug = true
-+opt-level = 3
-+incremental = true
-+
-+[profile.bench]
-+debug = 1
-+opt-level = 3
-+incremental = true
--- 
-2.50.1
-

From e44da234c71645b9bbecbe724bca473e0d951bb3 Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 11:11:45 -0400
Subject: [PATCH 16/21] Fix the debug_assert in bytes_in_context

---
 src/common.rs | 22 ++++++----------------
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/src/common.rs b/src/common.rs
index b9b6e51d3b8..2e6fcf29bba 100644
--- a/src/common.rs
+++ b/src/common.rs
@@ -58,17 +58,12 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
     // or is it using a more efficient representation?
     match bytes.len() % 8 {
         0 => {
-            debug_assert_eq!(
-                bytes.len() % 8,
-                0,
-                "bytes length is not a multiple of 8, so bytes.as_chunks will have a remainder"
-            );
             let context = &cx.context;
             let byte_type = context.new_type::<u64>();
             let typ = new_array_type(context, None, byte_type, bytes.len() as u64 / 8);
-            let elements: Vec<_> = bytes
-                .as_chunks::<8>()
-                .0
+            let (arrays, remainder) = bytes.as_chunks::<8>();
+            debug_assert!(remainder.is_empty());
+            let elements: Vec<_> = arrays
                 .iter()
                 .map(|&arr| {
                     context.new_rvalue_from_long(
@@ -85,17 +80,12 @@ pub fn bytes_in_context<'gcc, 'tcx>(cx: &CodegenCx<'gcc, 'tcx>, bytes: &[u8]) ->
             context.new_array_constructor(None, typ, &elements)
         }
         4 => {
-            debug_assert_eq!(
-                bytes.len() % 4,
-                0,
-                "bytes length is not a multiple of 4, so bytes.as_chunks will have a remainder"
-            );
             let context = &cx.context;
             let byte_type = context.new_type::<u32>();
             let typ = new_array_type(context, None, byte_type, bytes.len() as u64 / 4);
-            let elements: Vec<_> = bytes
-                .as_chunks::<4>()
-                .0
+            let (arrays, remainder) = bytes.as_chunks::<4>();
+            debug_assert!(remainder.is_empty());
+            let elements: Vec<_> = arrays
                 .iter()
                 .map(|&arr| {
                     context.new_rvalue_from_int(

From 2c9b73d97dbf4a0671b38f0c898de695124f94d1 Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 11:36:16 -0400
Subject: [PATCH 17/21] Add failing UI tests

---
 tests/failing-ui-tests.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tests/failing-ui-tests.txt b/tests/failing-ui-tests.txt
index e8a26a90890..da6544bb76d 100644
--- a/tests/failing-ui-tests.txt
+++ b/tests/failing-ui-tests.txt
@@ -110,4 +110,8 @@ tests/ui/eii/static/cross_crate_decl.rs
 tests/ui/eii/static/cross_crate_def.rs
 tests/ui/eii/static/same_address.rs
 tests/ui/eii/static/simple.rs
+tests/ui/eii/static/default.rs
+tests/ui/eii/static/default_cross_crate.rs
+tests/ui/eii/static/default_explicit.rs
+tests/ui/eii/static/default_cross_crate_explicit.rs
 tests/ui/explicit-tail-calls/default-trait-method.rs

From 34418c3d04f13c3753d543a2e4066be8be364d2b Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 11:37:24 -0400
Subject: [PATCH 18/21] Add spelling exclusion

---
 tools/cspell_dicts/rustc_codegen_gcc.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/cspell_dicts/rustc_codegen_gcc.txt b/tools/cspell_dicts/rustc_codegen_gcc.txt
index 619221d5260..794ebec11c3 100644
--- a/tools/cspell_dicts/rustc_codegen_gcc.txt
+++ b/tools/cspell_dicts/rustc_codegen_gcc.txt
@@ -65,6 +65,7 @@ riscv
 rlib
 roundevenf
 rustc
+sgpr
 sitofp
 sizet
 spir
@@ -75,5 +76,7 @@ uitofp
 unord
 uninlined
 utrunc
+vgpr
 xabort
+xtensa
 zext

From 2d86197160b7f6d60a2e05273f36315adc9f50fc Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 13:04:21 -0400
Subject: [PATCH 19/21] Add dummy implementation of more tile intrinsics

---
 src/intrinsic/llvm.rs | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/src/intrinsic/llvm.rs b/src/intrinsic/llvm.rs
index b19f63dd077..e28b15c708d 100644
--- a/src/intrinsic/llvm.rs
+++ b/src/intrinsic/llvm.rs
@@ -1662,37 +1662,62 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.ldtilecfg" => "__builtin_trap",
         "llvm.x86.sttilecfg" => "__builtin_trap",
         "llvm.x86.tileloadd64" => "__builtin_trap",
+        "llvm.x86.tileloadd64.internal" => "__builtin_trap",
         "llvm.x86.tilerelease" => "__builtin_trap",
         "llvm.x86.tilestored64" => "__builtin_trap",
+        "llvm.x86.tilestored64.internal" => "__builtin_trap",
         "llvm.x86.tileloaddrs64" => "__builtin_trap",
+        "llvm.x86.tileloaddrs64.internal" => "__builtin_trap",
         "llvm.x86.tileloaddt164" => "__builtin_trap",
+        "llvm.x86.tileloaddt164.internal" => "__builtin_trap",
         "llvm.x86.tileloaddrst164" => "__builtin_trap",
+        "llvm.x86.tileloaddrst164.internal" => "__builtin_trap",
         "llvm.x86.tilezero" => "__builtin_trap",
+        "llvm.x86.tilezero.internal" => "__builtin_trap",
         "llvm.x86.tilemovrow" => "__builtin_trap",
+        "llvm.x86.tilemovrow.internal" => "__builtin_trap",
         "llvm.x86.tilemovrowi" => "__builtin_trap",
         "llvm.x86.tdpbhf8ps" => "__builtin_trap",
+        "llvm.x86.tdpbhf8ps.internal" => "__builtin_trap",
         "llvm.x86.tdphbf8ps" => "__builtin_trap",
+        "llvm.x86.tdphbf8ps.internal" => "__builtin_trap",
         "llvm.x86.tdpbf8ps" => "__builtin_trap",
+        "llvm.x86.tdpbf8ps.internal" => "__builtin_trap",
         "llvm.x86.tdphf8ps" => "__builtin_trap",
+        "llvm.x86.tdphf8ps.internal" => "__builtin_trap",
         "llvm.x86.tdpbf16ps" => "__builtin_trap",
+        "llvm.x86.tdpbf16ps.internal" => "__builtin_trap",
         "llvm.x86.tdpbssd" => "__builtin_trap",
+        "llvm.x86.tdpbssd.internal" => "__builtin_trap",
         "llvm.x86.tdpbsud" => "__builtin_trap",
+        "llvm.x86.tdpbsud.internal" => "__builtin_trap",
         "llvm.x86.tdpbusd" => "__builtin_trap",
+        "llvm.x86.tdpbusd.internal" => "__builtin_trap",
         "llvm.x86.tdpbuud" => "__builtin_trap",
+        "llvm.x86.tdpbuud.internal" => "__builtin_trap",
         "llvm.x86.tdpfp16ps" => "__builtin_trap",
+        "llvm.x86.tdpfp16ps.internal" => "__builtin_trap",
         "llvm.x86.tmmultf32ps" => "__builtin_trap",
+        "llvm.x86.tmmultf32ps.internal" => "__builtin_trap",
         "llvm.x86.tcvtrowps2phh" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2phh.internal" => "__builtin_trap",
         "llvm.x86.tcvtrowps2phl" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2phl.internal" => "__builtin_trap",
         "llvm.x86.tcvtrowd2ps" => "__builtin_trap",
+        "llvm.x86.tcvtrowd2ps.internal" => "__builtin_trap",
         "llvm.x86.tcvtrowd2psi" => "__builtin_trap",
         "llvm.x86.tcvtrowps2phhi" => "__builtin_trap",
         "llvm.x86.tcvtrowps2phli" => "__builtin_trap",
         "llvm.x86.tcvtrowps2bf16h" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2bf16h.internal" => "__builtin_trap",
         "llvm.x86.tcvtrowps2bf16hi" => "__builtin_trap",
         "llvm.x86.tcvtrowps2bf16l" => "__builtin_trap",
+        "llvm.x86.tcvtrowps2bf16l.internal" => "__builtin_trap",
         "llvm.x86.tcvtrowps2bf16li" => "__builtin_trap",
         "llvm.x86.tcmmimfp16ps" => "__builtin_trap",
+        "llvm.x86.tcmmimfp16ps.internal" => "__builtin_trap",
         "llvm.x86.tcmmrlfp16ps" => "__builtin_trap",
+        "llvm.x86.tcmmrlfp16ps.internal" => "__builtin_trap",
 
         // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
         _ => map_arch_intrinsic(name),

From cf908180f397288070c022adac6ad953fbe0bcc4 Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 14:37:37 -0400
Subject: [PATCH 20/21] Ignore more tile intrinsic tests

---
 .github/workflows/stdarch.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/stdarch.yml b/.github/workflows/stdarch.yml
index a437f06a465..3d2ffa57dff 100644
--- a/.github/workflows/stdarch.yml
+++ b/.github/workflows/stdarch.yml
@@ -95,8 +95,8 @@ jobs:
       if: ${{ matrix.cargo_runner }}
       run: |
         # FIXME: these tests fail when the sysroot is compiled with LTO because of a missing symbol in proc-macro.
-        # FIXME: remove --skip test_tile_ when it's implemented.
-        STDARCH_TEST_SKIP_FUNCTION="xsave,xsaveopt,xsave64,xsaveopt64" STDARCH_TEST_EVERYTHING=1 CHANNEL=release CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="${{ matrix.cargo_runner }}" TARGET=x86_64-unknown-linux-gnu CG_RUSTFLAGS="-Ainternal_features" ./y.sh cargo test --manifest-path build/build_sysroot/sysroot_src/library/stdarch/Cargo.toml -- --skip rtm --skip tbm --skip sse4a --skip test_tile_
+        # FIXME: remove --skip test_tile_ and --skip --skip test__tile when it's implemented.
+        STDARCH_TEST_SKIP_FUNCTION="xsave,xsaveopt,xsave64,xsaveopt64" STDARCH_TEST_EVERYTHING=1 CHANNEL=release CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="${{ matrix.cargo_runner }}" TARGET=x86_64-unknown-linux-gnu CG_RUSTFLAGS="-Ainternal_features" ./y.sh cargo test --manifest-path build/build_sysroot/sysroot_src/library/stdarch/Cargo.toml -- --skip rtm --skip tbm --skip sse4a --skip test_tile_ --skip test__tile
 
   # Summary job for the merge queue.
   # ALL THE PREVIOUS JOBS NEED TO BE ADDED TO THE `needs` SECTION OF THIS JOB!

From adc448406245d5cd18efe73c5905de17f0902f23 Mon Sep 17 00:00:00 2001
From: Antoni Boucher <bouanto@zoho.com>
Date: Sun, 28 Jun 2026 14:42:06 -0400
Subject: [PATCH 21/21] Add dummy implementation of f16 for m68k CI

---
 src/type_.rs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/type_.rs b/src/type_.rs
index 5252f93a92e..514bcbe3bff 100644
--- a/src/type_.rs
+++ b/src/type_.rs
@@ -153,7 +153,7 @@ impl<'gcc, 'tcx> BaseTypeCodegenMethods for CodegenCx<'gcc, 'tcx> {
         if self.supports_f16_type {
             return self.context.new_c_type(CType::Float16);
         }
-        bug!("unsupported float width 16")
+        self.u16_type
     }
 
     fn type_f32(&self) -> Type<'gcc> {