diff --git a/.github/workflows/event-pull_request.yml b/.github/workflows/event-pull_request.yml
index 1dba65a53..af1be19a6 100644
--- a/.github/workflows/event-pull_request.yml
+++ b/.github/workflows/event-pull_request.yml
@@ -70,6 +70,10 @@ jobs:
     uses: ./.github/workflows/codeql-analysis.yml
     secrets: inherit
 
+  spaces-isa-baseline:
+    uses: ./.github/workflows/spaces-isa-baseline.yml
+    secrets: inherit
+
   spellcheck:
     runs-on: ubuntu-latest
     steps:
@@ -88,6 +92,7 @@ jobs:
       - sanitizer
       - coverage
       - codeql-analysis
+      - spaces-isa-baseline
       - spellcheck
     runs-on: ubuntu-latest
     if: ${{ !cancelled() }}
diff --git a/.github/workflows/spaces-isa-baseline.yml b/.github/workflows/spaces-isa-baseline.yml
new file mode 100644
index 000000000..7527c72e4
--- /dev/null
+++ b/.github/workflows/spaces-isa-baseline.yml
@@ -0,0 +1,77 @@
+name: spaces ISA baseline guard
+
+# These jobs assert negatives: that configuring with an ISA-raising flag injected through CXXFLAGS
+# makes CMake fail, because src/VecSim/spaces/CMakeLists.txt rejects it. They are kept separate
+# from the main build jobs, since a green run here proves nothing about the build itself, only that
+# each rejection still fires. Every case below was a real bypass at some point in review, so a case
+# that stops failing is a regression, not a cleanup opportunity.
+
+on: [workflow_call, workflow_dispatch]
+
+jobs:
+  reject-isa-override:
+    name: "configure must fail: CXXFLAGS=${{ matrix.flag }}"
+    runs-on: ubuntu-latest
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          # A native baseline is unknown at build time, so it can raise the fallback's ISA above
+          # any deployment CPU.
+          - flag: -march=native
+          - flag: -mtune=native
+          - flag: -mcpu=native
+          # An explicit feature flag is NOT cancelled by a later -march= baseline: measured on
+          # gcc 13, "-mavx2 ... -march=x86-64" still emitted hundreds of AVX instructions into the
+          # scalar fallback.
+          - flag: -mavx2
+          - flag: -mavx512f
+          - flag: -mfma
+    steps:
+      - name: checkout
+        uses: actions/checkout@v6
+        with:
+          submodules: recursive
+      - name: assert configure fails on an inherited ${{ matrix.flag }}
+        env:
+          CXXFLAGS: ${{ matrix.flag }}
+        run: |
+          set +e
+          output=$(cmake -S . -B build-reject -DVECSIM_BUILD_TESTS=OFF 2>&1)
+          status=$?
+          echo "$output"
+          set -e
+          if [ "$status" -eq 0 ]; then
+            echo "Expected the configure to fail because of the inherited ${{ matrix.flag }}, but it succeeded."
+            exit 1
+          fi
+          if ! echo "$output" | grep -q -- "Refusing to configure"; then
+            echo "Configure failed, but not with the expected rejection message."
+            exit 1
+          fi
+
+  accept-explicit-baseline:
+    name: "configure must succeed and warn: CXXFLAGS=-march=x86-64-v2"
+    runs-on: ubuntu-latest
+    steps:
+      - name: checkout
+        uses: actions/checkout@v6
+        with:
+          submodules: recursive
+      - name: assert an explicit non-native baseline still configures
+        env:
+          CXXFLAGS: -march=x86-64-v2
+        run: |
+          set +e
+          output=$(cmake -S . -B build-accept -DVECSIM_BUILD_TESTS=OFF 2>&1)
+          status=$?
+          echo "$output"
+          set -e
+          if [ "$status" -ne 0 ]; then
+            echo "A consumer declaring a legitimate deployment floor must still be able to build."
+            exit 1
+          fi
+          if ! echo "$output" | grep -qi "baseline"; then
+            echo "Expected a warning naming the baseline, so the difference is not silent."
+            exit 1
+          fi
diff --git a/cmake/tier_probe.cmake b/cmake/tier_probe.cmake
new file mode 100644
index 000000000..40df4d625
--- /dev/null
+++ b/cmake/tier_probe.cmake
@@ -0,0 +1,77 @@
+# Probe whether the current toolchain can actually build a SIMD tier, instead of inferring the
+# toolchain's capability from a side channel (a compiler flag check alone, or a binutils version
+# table). CHECK_CXX_COMPILER_FLAG only asks the compiler whether it recognizes a flag; it does
+# not ask whether the compiler and assembler can carry a real translation unit through to a
+# finished object under the tier's complete flag combination. This probe does that: it
+# try_compiles the tier's own source file under the tier's own flags, so a flag combination that
+# the compiler accepts individually but rejects together, or a flag whose instructions the
+# assembler cannot emit, fails here rather than reaching the build.
+#
+#   vecsim_tier_compiles(<result_var> SOURCE <path> FLAGS <flag string> [NAME <label>])
+#
+# Sets <result_var> to true/false depending on whether <path> compiles under <flag string>.
+# Callers should define each tier's flag string once in a variable and pass that same variable
+# both here and to set_source_files_properties(), so the probe can never test a different flag
+# set than the one the build actually uses.
+
+include(CheckCXXCompilerFlag)
+
+function(vecsim_tier_compiles result_var)
+	set(_one_value_args SOURCE FLAGS NAME)
+	cmake_parse_arguments(_tier_probe "" "${_one_value_args}" "" ${ARGN})
+
+	if(NOT _tier_probe_SOURCE)
+		message(FATAL_ERROR "vecsim_tier_compiles: SOURCE is required")
+	endif()
+	if(NOT _tier_probe_NAME)
+		set(_tier_probe_NAME "${_tier_probe_SOURCE}")
+	endif()
+
+	# The cache variable name follows the same idea CHECK_CXX_COMPILER_FLAG relies on (cache the
+	# answer under a name that identifies what was asked), extended here with the compiler
+	# identity/version and the flag string themselves, so a compiler upgrade or an edit to the
+	# tier's flags cannot reuse a stale answer computed under a different compiler or different
+	# flags.
+	string(MAKE_C_IDENTIFIER
+		"TIER_COMPILES_${_tier_probe_NAME}_${CMAKE_CXX_COMPILER_ID}_${CMAKE_CXX_COMPILER_VERSION}_${_tier_probe_FLAGS}"
+		_tier_probe_cache_var)
+
+	if(NOT DEFINED ${_tier_probe_cache_var})
+		# Resolve relative to the caller's source directory (functions/*.cpp is written relative
+		# to src/VecSim/spaces/CMakeLists.txt), since try_compile does not carry that context.
+		get_filename_component(_tier_probe_source_abs "${_tier_probe_SOURCE}" ABSOLUTE)
+
+		# cpu_features arrives via FetchContent_MakeAvailable(cpu_features) in
+		# cmake/cpu_features.cmake, included before any tier block runs, so the target exists
+		# here. Read its include directory from the target itself rather than hardcoding a path
+		# under the FetchContent _deps tree, which is an implementation detail that can move.
+		get_target_property(_tier_probe_cpu_features_dir cpu_features SOURCE_DIR)
+
+		# The tier translation units have no main(): they are dispatch kernels selected at
+		# runtime, not entry points. A default try_compile probe builds an executable and would
+		# fail to LINK for every tier for that reason alone, which would silently disable the
+		# whole dispatch layer while still reporting a successful configure. Building a static
+		# library instead only requires the tier's own translation unit to compile and assemble.
+		set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+
+		try_compile(${_tier_probe_cache_var}
+			"${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/tier_probe/${_tier_probe_cache_var}"
+			SOURCES "${_tier_probe_source_abs}"
+			CMAKE_FLAGS
+				"-DINCLUDE_DIRECTORIES:STRING=${root}/src;${_tier_probe_cpu_features_dir}/include"
+			COMPILE_DEFINITIONS "${_tier_probe_FLAGS}"
+			CXX_STANDARD ${CMAKE_CXX_STANDARD}
+			CXX_STANDARD_REQUIRED ON
+			OUTPUT_VARIABLE _tier_probe_output
+		)
+
+		if(NOT ${_tier_probe_cache_var})
+			message(STATUS "Skipping tier ${_tier_probe_NAME}: toolchain failed to compile "
+				"${_tier_probe_SOURCE} with '${_tier_probe_FLAGS}'. A tier that cannot compile "
+				"on this toolchain is expected on some machines; the runtime degrades to a "
+				"lower tier.")
+		endif()
+	endif()
+
+	set(${result_var} ${${_tier_probe_cache_var}} PARENT_SCOPE)
+endfunction()
diff --git a/cmake/vecsim_manifest.cmake b/cmake/vecsim_manifest.cmake
new file mode 100644
index 000000000..3d39afc7f
--- /dev/null
+++ b/cmake/vecsim_manifest.cmake
@@ -0,0 +1,154 @@
+# Reads spaces/isa_features.def and spaces/isa_tiers.def and turns them into CMake variables, so the
+# manifests are the single place that says what a tier is. Nothing here decides policy: every value
+# comes from a manifest row, and a row that names something the other manifest does not define is a
+# configure error rather than a silently skipped tier.
+#
+#   vecsim_load_manifests(<features.def> <tiers.def>)
+#     VECSIM_FEATURE_TOKENS                  all tokens
+#     VECSIM_FEATURE_<TOK>_{ARCH,FRAGMENT,LEVEL,FIELD}
+#     VECSIM_TIERS                           all tiers, in manifest order
+#     VECSIM_TIER_<T>_{ARCH,STEM,PRIORITY,FLAG_TOKENS,GUARANTEE_TOKENS}
+#
+#   vecsim_tier_flags(<out_var> <tier>)      the compile flag string derived from FLAG_TOKENS alone
+#
+# The flag string is derived; the runtime predicate is not. GUARANTEE_TOKENS is carried through
+# untouched for the C++ side to fold into TierInfo<T>::supported(), because a flag fragment expands
+# to a compiler-defined bundle that differs between compilers for the same -march string. Deriving a
+# predicate from flags would reintroduce exactly that unsoundness.
+
+# ARM -march levels, low to high. A tier's level is the highest among its tokens, because ARM -march
+# strings are monolithic: one level plus "+feature" suffixes, not a union of independent options.
+set(VECSIM_ARM_LEVELS "armv8-a;armv8.1-a;armv8.2-a;armv8.3-a;armv8.4-a;armv8.5-a;armv8.6-a;armv9-a")
+
+function(_vecsim_arm_level_rank out_var level)
+	list(FIND VECSIM_ARM_LEVELS "${level}" _rank)
+	if(_rank EQUAL -1)
+		message(FATAL_ERROR
+			"vecsim manifest: unknown ARM architecture level '${level}'. Add it to "
+			"VECSIM_ARM_LEVELS in cmake/vecsim_manifest.cmake, in ascending order, so the "
+			"highest-level comparison stays meaningful.")
+	endif()
+	set(${out_var} ${_rank} PARENT_SCOPE)
+endfunction()
+
+function(vecsim_load_manifests features_def tiers_def)
+	if(NOT EXISTS "${features_def}")
+		message(FATAL_ERROR "vecsim manifest: cannot read ${features_def}")
+	endif()
+	if(NOT EXISTS "${tiers_def}")
+		message(FATAL_ERROR "vecsim manifest: cannot read ${tiers_def}")
+	endif()
+
+	set(_tokens "")
+	file(STRINGS "${features_def}" _lines)
+	foreach(_line IN LISTS _lines)
+		if(_line MATCHES "^FEATURE\\( *([A-Za-z0-9_]+) *, *([A-Z0-9]+) *, *\"([^\"]*)\" *, *([^ ,]+) *, *([A-Za-z0-9_]+) *\\)")
+			set(_tok "${CMAKE_MATCH_1}")
+			list(APPEND _tokens "${_tok}")
+			set(VECSIM_FEATURE_${_tok}_ARCH     "${CMAKE_MATCH_2}" PARENT_SCOPE)
+			set(VECSIM_FEATURE_${_tok}_FRAGMENT "${CMAKE_MATCH_3}" PARENT_SCOPE)
+			set(VECSIM_FEATURE_${_tok}_LEVEL    "${CMAKE_MATCH_4}" PARENT_SCOPE)
+			set(VECSIM_FEATURE_${_tok}_FIELD    "${CMAKE_MATCH_5}" PARENT_SCOPE)
+			# also visible inside this function, for the validation below
+			set(VECSIM_FEATURE_${_tok}_ARCH     "${CMAKE_MATCH_2}")
+			set(VECSIM_FEATURE_${_tok}_FRAGMENT "${CMAKE_MATCH_3}")
+			set(VECSIM_FEATURE_${_tok}_LEVEL    "${CMAKE_MATCH_4}")
+		endif()
+	endforeach()
+	if(NOT _tokens)
+		message(FATAL_ERROR "vecsim manifest: ${features_def} defined no FEATURE rows. A parser that "
+			"silently reads zero rows would disable every tier while the configure still succeeded.")
+	endif()
+
+	set(_tiers "")
+	file(STRINGS "${tiers_def}" _lines)
+	foreach(_line IN LISTS _lines)
+		if(_line MATCHES "^TIER\\( *([A-Za-z0-9_]+) *, *([A-Z0-9]+) *, *([A-Za-z0-9_.]+) *, *([0-9]+) *, *\\(([^)]*)\\) *, *\\(([^)]*)\\) *\\)")
+			set(_tier "${CMAKE_MATCH_1}")
+			set(_arch "${CMAKE_MATCH_2}")
+			# The manifest separates tokens with commas for readability; CMake lists are
+			# semicolon-separated, so convert rather than relying on a comma string behaving
+			# like a list (it does not, and foreach(IN LISTS) silently sees one element).
+			string(REPLACE " " "" _flag_tokens "${CMAKE_MATCH_5}")
+			string(REPLACE "," ";" _flag_tokens "${_flag_tokens}")
+			string(REPLACE " " "" _guar_tokens "${CMAKE_MATCH_6}")
+			string(REPLACE "," ";" _guar_tokens "${_guar_tokens}")
+			list(APPEND _tiers "${_tier}")
+
+			# Validate before exporting, so a typo is a configure error and not a missing tier.
+			foreach(_t IN LISTS _flag_tokens _guar_tokens)
+				list(FIND _tokens "${_t}" _known)
+				if(_known EQUAL -1)
+					message(FATAL_ERROR
+						"vecsim manifest: tier ${_tier} names feature token '${_t}', which has no "
+						"FEATURE row in ${features_def}.")
+				endif()
+				if(NOT "${VECSIM_FEATURE_${_t}_ARCH}" STREQUAL "${_arch}")
+					message(FATAL_ERROR
+						"vecsim manifest: tier ${_tier} is ${_arch} but names token '${_t}', which "
+						"is ${VECSIM_FEATURE_${_t}_ARCH}. A tier may only name tokens of its own "
+						"architecture.")
+				endif()
+			endforeach()
+
+			set(VECSIM_TIER_${_tier}_ARCH             "${_arch}"          PARENT_SCOPE)
+			set(VECSIM_TIER_${_tier}_STEM             "${CMAKE_MATCH_3}"  PARENT_SCOPE)
+			set(VECSIM_TIER_${_tier}_PRIORITY         "${CMAKE_MATCH_4}"  PARENT_SCOPE)
+			set(VECSIM_TIER_${_tier}_FLAG_TOKENS      "${_flag_tokens}"   PARENT_SCOPE)
+			set(VECSIM_TIER_${_tier}_GUARANTEE_TOKENS "${_guar_tokens}"   PARENT_SCOPE)
+		endif()
+	endforeach()
+	if(NOT _tiers)
+		message(FATAL_ERROR "vecsim manifest: ${tiers_def} defined no TIER rows.")
+	endif()
+
+	set(VECSIM_FEATURE_TOKENS "${_tokens}" PARENT_SCOPE)
+	set(VECSIM_TIERS          "${_tiers}"  PARENT_SCOPE)
+endfunction()
+
+# Derive a tier's compile flags from its FLAG_TOKENS. x86 unions the -m fragments in token order;
+# ARM emits one -march at the highest level in the token list, then each distinct fragment.
+function(vecsim_tier_flags out_var tier)
+	set(_arch "${VECSIM_TIER_${tier}_ARCH}")
+	set(_tokens "${VECSIM_TIER_${tier}_FLAG_TOKENS}")
+
+	if("${_arch}" STREQUAL "X86")
+		set(_parts "")
+		foreach(_t IN LISTS _tokens)
+			set(_frag "${VECSIM_FEATURE_${_t}_FRAGMENT}")
+			list(FIND _parts "${_frag}" _dup)
+			if(_frag AND _dup EQUAL -1)
+				list(APPEND _parts "${_frag}")
+			endif()
+		endforeach()
+		string(JOIN " " _flags ${_parts})
+	elseif("${_arch}" STREQUAL "ARM")
+		set(_best_level "armv8-a")
+		_vecsim_arm_level_rank(_best_rank "${_best_level}")
+		foreach(_t IN LISTS _tokens)
+			set(_level "${VECSIM_FEATURE_${_t}_LEVEL}")
+			if(NOT "${_level}" STREQUAL "-")
+				_vecsim_arm_level_rank(_rank "${_level}")
+				if(_rank GREATER _best_rank)
+					set(_best_rank ${_rank})
+					set(_best_level "${_level}")
+				endif()
+			endif()
+		endforeach()
+		set(_suffix "")
+		set(_seen "")
+		foreach(_t IN LISTS _tokens)
+			set(_frag "${VECSIM_FEATURE_${_t}_FRAGMENT}")
+			list(FIND _seen "${_frag}" _dup)
+			if(_frag AND _dup EQUAL -1)
+				list(APPEND _seen "${_frag}")
+				string(APPEND _suffix "${_frag}")
+			endif()
+		endforeach()
+		set(_flags "-march=${_best_level}${_suffix}")
+	else()
+		message(FATAL_ERROR "vecsim manifest: tier ${tier} has unknown architecture '${_arch}'")
+	endif()
+
+	set(${out_var} "${_flags}" PARENT_SCOPE)
+endfunction()
diff --git a/src/VecSim/spaces/CMakeLists.txt b/src/VecSim/spaces/CMakeLists.txt
index eb8a15fdd..0e5207665 100644
--- a/src/VecSim/spaces/CMakeLists.txt
+++ b/src/VecSim/spaces/CMakeLists.txt
@@ -13,7 +13,130 @@ set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -Werror -Wall")
 
 set(OPTIMIZATIONS "")
 
+# --------------------------------------------------------------------------------------------
+# Conservative architecture baseline for the scalar fallback.
+#
+# VectorSimilaritySpaces_no_optimization (L2/L2.cpp, IP/IP.cpp) is the scalar fallback that
+# runtime dispatch degrades to when the CPU lacks a tier's required features, and the only
+# implementation that must run on every deployment CPU. The root CMakeLists.txt repeatedly
+# appends to whatever CMAKE_CXX_FLAGS it inherits, and consumers export CXXFLAGS into this
+# build (RediSearch's build.sh does), so an inherited -march=native would silently let the
+# compiler auto-vectorize the fallback itself with instructions the deployment CPU may not
+# have, defeating runtime dispatch in the one place that must be universally safe. Pin a
+# conservative baseline per target architecture below, and refuse to configure if something
+# upstream already raised it.
+include(CheckCXXCompilerFlag)
+
+# SPACES_ARCH_FAMILY is computed once here from CMAKE_SYSTEM_PROCESSOR so the two arch regexes
+# below are not repeated again at the tier-gating if() blocks further down (x86_64 tiers and ARM
+# tiers each used to re-run the same MATCHES check). Everything downstream branches on this
+# variable instead of re-matching CMAKE_SYSTEM_PROCESSOR.
+set(SPACES_ARCH_FAMILY "")
 if(CMAKE_SYSTEM_PROCESSOR MATCHES "(x86_64)|(AMD64|amd64)|(^i.86$)")
+	set(SPACES_ARCH_FAMILY "x86_64")
+elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv.*)")
+	set(SPACES_ARCH_FAMILY "aarch64")
+endif()
+
+set(SPACES_BASELINE_ARCH_FLAG "")
+set(SPACES_BASELINE_VALUE "")
+if(SPACES_ARCH_FAMILY STREQUAL "x86_64")
+	CHECK_CXX_COMPILER_FLAG(-march=x86-64 CXX_BASELINE_X86_64)
+	if(CXX_BASELINE_X86_64)
+		set(SPACES_BASELINE_VALUE "x86-64")
+		set(SPACES_BASELINE_ARCH_FLAG "-march=${SPACES_BASELINE_VALUE}")
+	endif()
+elseif(SPACES_ARCH_FAMILY STREQUAL "aarch64")
+	CHECK_CXX_COMPILER_FLAG(-march=armv8-a CXX_BASELINE_ARMV8A)
+	if(CXX_BASELINE_ARMV8A)
+		set(SPACES_BASELINE_VALUE "armv8-a")
+		set(SPACES_BASELINE_ARCH_FLAG "-march=${SPACES_BASELINE_VALUE}")
+	endif()
+endif()
+# Any other architecture keeps an empty baseline: adding nothing is safer than guessing a flag
+# the compiler may reject.
+#
+# On x86_64 and aarch64, though, the baseline flag probed above is supported by every gcc and clang
+# that can build this library, so a failed probe never means "this compiler lacks the flag". It
+# means something in the inherited flags made the probe fail. CHECK_CXX_COMPILER_FLAG compiles its
+# test with CMAKE_CXX_FLAGS included and treats any warning that names a flag as failure, so an
+# inherited -mcpu=neoverse-n1 makes gcc emit
+#   switch '-mcpu=neoverse-n1' conflicts with '-march=armv8-a' switch
+# and the probe reports Failed. Failing open there would silently drop the baseline from the scalar
+# fallback while the configure still succeeded, which is the exact hazard this block exists to
+# prevent, so fail closed instead and name the likely cause.
+if(SPACES_ARCH_FAMILY STREQUAL "x86_64" OR SPACES_ARCH_FAMILY STREQUAL "aarch64")
+	if(SPACES_BASELINE_ARCH_FLAG STREQUAL "")
+		message(FATAL_ERROR
+			"Could not establish a conservative ISA baseline on ${SPACES_ARCH_FAMILY}: the probe "
+			"for the baseline -march flag failed. Refusing to configure, because continuing would "
+			"leave the scalar fallback (VectorSimilaritySpaces_no_optimization) compiled with "
+			"whatever ISA the inherited flags imply, defeating runtime dispatch on any deployment "
+			"CPU that lacks it. The usual cause is an inherited -mcpu= or -march= in CMAKE_CXX_FLAGS "
+			"or CXXFLAGS that conflicts with the baseline flag: the probe compiles with those flags "
+			"present and counts a conflict warning as failure. Current CMAKE_CXX_FLAGS: "
+			"'${CMAKE_CXX_FLAGS}'.")
+	endif()
+endif()
+
+# A native baseline (auto-detected from the build machine, so its instruction set is unknown
+# ahead of time) is rejected outright below: it would let the compiler vectorize the scalar
+# fallback with instructions the deployment CPU may lack, defeating runtime dispatch, and there
+# is no safe way to honor it. An explicit non-native -march/-mcpu that merely differs from the
+# baseline chosen above is a deliberate, known deployment floor (for example -march=x86-64-v2,
+# now a distro default, or -mcpu=neoverse-n1), so it only gets a warning: the target-level
+# baseline applied further down with target_compile_options() still keeps the scalar fallback
+# on the conservative baseline regardless, and the per-tier source-level flags still win for the
+# functions/*.cpp tiers, so the value is respected everywhere else it is meant to apply.
+# -mtune is deliberately not checked: it only changes instruction scheduling, not which
+# instructions are legal, so a non-native -mtune does not threaten the invariant and rejecting
+# it would break legitimate consumer builds.
+function(_spaces_reject_isa_override description flags_string)
+	if("${flags_string}" STREQUAL "")
+		return()
+	endif()
+	separate_arguments(_flags UNIX_COMMAND "${flags_string}")
+	foreach(_flag ${_flags})
+		if(_flag MATCHES "^-m(arch|tune|cpu)=native$")
+			message(FATAL_ERROR
+				"Found '${_flag}' in ${description}. Refusing to configure: this library is "
+				"built on one machine and run on another, so a native ISA baseline would let "
+				"the compiler vectorize the scalar fallback (VectorSimilaritySpaces_no_optimization) "
+				"with instructions the deployment CPU may lack, defeating runtime dispatch. "
+				"Remove '${_flag}' from ${description}.")
+		elseif(_flag MATCHES "^-m(mmx|3dnow[a-z]*|sse[0-9a-z_.]*|avx[0-9a-z_.]*|fma[0-9a-z_.]*|f16c|bmi[0-9]*|abm|lzcnt|popcnt|aes|vaes|sha|pclmul|gfni|xop|amx[-a-z0-9_]*|fp16|dotprod|crypto|simd)$")
+			message(FATAL_ERROR
+				"Found '${_flag}' in ${description}. Refusing to configure: an explicit ISA "
+				"feature flag enables those instructions directly and a later -march= baseline "
+				"does NOT cancel it. Measured on gcc 13: '-mavx2 ... -march=x86-64' still emitted "
+				"hundreds of AVX instructions into the scalar fallback "
+				"(VectorSimilaritySpaces_no_optimization), which is the one implementation runtime "
+				"dispatch degrades to when the CPU lacks everything else, so the fallback itself "
+				"would fault on a deployment CPU without ${_flag}'s instructions. There is no "
+				"reliable way to neutralize it, so remove '${_flag}' from ${description}. Disabling "
+				"forms (-mno-...) are not affected, and -mtune= is fine: it changes scheduling, not "
+				"which instructions are legal.")
+		elseif(_flag MATCHES "^-m(arch|cpu)=(.+)$")
+			if(NOT SPACES_BASELINE_VALUE STREQUAL "" AND NOT CMAKE_MATCH_2 STREQUAL SPACES_BASELINE_VALUE)
+				message(WARNING
+					"Found '${_flag}' in ${description}, which differs from the baseline "
+					"'${SPACES_BASELINE_ARCH_FLAG}' this build would otherwise pick. The conservative "
+					"baseline is still applied to the scalar fallback "
+					"(VectorSimilaritySpaces_no_optimization), so it stays safe; '${_flag}' is "
+					"respected everywhere else.")
+			endif()
+		endif()
+	endforeach()
+endfunction()
+
+_spaces_reject_isa_override("CMAKE_CXX_FLAGS" "${CMAKE_CXX_FLAGS}")
+if(CMAKE_BUILD_TYPE)
+	string(TOUPPER "${CMAKE_BUILD_TYPE}" _spaces_build_type_upper)
+	_spaces_reject_isa_override("CMAKE_CXX_FLAGS_${_spaces_build_type_upper}" "${CMAKE_CXX_FLAGS_${_spaces_build_type_upper}}")
+endif()
+_spaces_reject_isa_override("the CXXFLAGS environment variable" "$ENV{CXXFLAGS}")
+
+if(SPACES_ARCH_FAMILY STREQUAL "x86_64")
 	# Check that the compiler supports instructions flag.
 	# from gcc14+ -mavx512bw is implicitly enabled when -mavx512vbmi2 is requested
 	include(${root}/cmake/x86_64InstructionFlags.cmake)
@@ -123,7 +246,7 @@ if(CMAKE_SYSTEM_PROCESSOR MATCHES "(x86_64)|(AMD64|amd64)|(^i.86$)")
 	endif()
 endif()
 
-if (CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv.*)")
+if (SPACES_ARCH_FAMILY STREQUAL "aarch64")
 	include(${root}/cmake/aarch64InstructionFlags.cmake)
 
 	# Create different optimization implementations for ARM architecture
@@ -181,6 +304,94 @@ if (CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv.*)")
 	endif()
 endif()
 
+# ---------------------------------------------------------------------------------------------
+# Manifest layer.
+#
+# The tier blocks above are still the ones that compile the tier translation units. This block adds
+# the manifest-derived view of the same facts, so the two can be compared, and exposes what the C++
+# dispatch layer needs: a 0-or-1 availability macro per tier and a generated umbrella header.
+#
+# The comparison is the point. While both descriptions exist, drift between them would be silent, so
+# every tier the blocks above compiled has its legacy COMPILE_FLAGS read back and asserted equal to
+# what the manifest derives. Nothing is duplicated by hand: the legacy side is read from the source
+# property that the build will actually use. When the last legacy chooser goes, the blocks above go
+# with it and this becomes the only description.
+include(${root}/cmake/vecsim_manifest.cmake)
+include(${root}/cmake/tier_probe.cmake)
+
+vecsim_load_manifests(
+	"${CMAKE_CURRENT_SOURCE_DIR}/isa_features.def"
+	"${CMAKE_CURRENT_SOURCE_DIR}/isa_tiers.def")
+
+# Availability is exposed on an internal interface target rather than as directory-scope
+# definitions, so the library and the tests see the same values and consumers of the installed
+# library see none of them. Directory scope was how OPT_* silently vanished from tests/unit once a
+# definition moved.
+add_library(vecsim_spaces_manifest INTERFACE)
+
+set(_manifest_arch "")
+if(SPACES_ARCH_FAMILY STREQUAL "x86_64")
+	set(_manifest_arch "X86")
+elseif(SPACES_ARCH_FAMILY STREQUAL "aarch64")
+	set(_manifest_arch "ARM")
+endif()
+
+set(_manifest_tier_includes "")
+foreach(_tier IN LISTS VECSIM_TIERS)
+	set(_tier_arch "${VECSIM_TIER_${_tier}_ARCH}")
+	set(_tier_stem "${VECSIM_TIER_${_tier}_STEM}")
+
+	if(NOT "${_tier_arch}" STREQUAL "${_manifest_arch}")
+		# A tier for the other architecture is not a failure and not a candidate. Define it as
+		# unavailable so if constexpr sees a value for every tier on every build.
+		target_compile_definitions(vecsim_spaces_manifest INTERFACE VECSIM_BUILT_${_tier}=0)
+		continue()
+	endif()
+
+	vecsim_tier_flags(_tier_flags "${_tier}")
+
+	# Did the legacy block above compile this tier, and with which flags?
+	get_source_file_property(_legacy_flags "functions/${_tier_stem}.cpp" COMPILE_FLAGS)
+	if(_legacy_flags)
+		# Normalise whitespace only: some legacy strings carry double spaces.
+		string(REGEX REPLACE "[ \t]+" " " _legacy_norm "${_legacy_flags}")
+		string(STRIP "${_legacy_norm}" _legacy_norm)
+		if(NOT "${_legacy_norm}" STREQUAL "${_tier_flags}")
+			message(FATAL_ERROR
+				"vecsim manifest: tier ${_tier} would be compiled with '${_legacy_norm}' by the "
+				"legacy block but the manifest derives '${_tier_flags}'. One of the two is wrong. "
+				"While both descriptions exist they must agree exactly, or the manifest is not "
+				"describing the build.")
+		endif()
+	endif()
+
+	# Buildability, asked the only way that answers the real question: can this toolchain carry
+	# this tier's own translation unit through to an object under this tier's own flags?
+	vecsim_tier_compiles(_tier_ok
+		SOURCE "functions/${_tier_stem}.cpp"
+		FLAGS "${_tier_flags}"
+		NAME "${_tier}")
+
+	if(_tier_ok)
+		target_compile_definitions(vecsim_spaces_manifest INTERFACE VECSIM_BUILT_${_tier}=1)
+		string(APPEND _manifest_tier_includes
+			"#include \"VecSim/spaces/functions/${_tier_stem}.h\"\n")
+	else()
+		target_compile_definitions(vecsim_spaces_manifest INTERFACE VECSIM_BUILT_${_tier}=0)
+		message(STATUS "Manifest: tier ${_tier} is unavailable on this toolchain")
+	endif()
+endforeach()
+
+# The umbrella is generated rather than hand-maintained, because a TIER() expansion cannot emit an
+# #include and a hand-synchronised list would need a checker to prove it matches the manifest. A
+# generated one cannot disagree with its source.
+file(GENERATE
+	OUTPUT "${CMAKE_CURRENT_BINARY_DIR}/generated/VecSim/spaces/functions/all_tiers.h"
+	CONTENT "// Generated from isa_tiers.def at configure time. Do not edit.\n\n#pragma once\n\n${_manifest_tier_includes}")
+target_include_directories(vecsim_spaces_manifest INTERFACE "${CMAKE_CURRENT_BINARY_DIR}/generated")
+
+# ---------------------------------------------------------------------------------------------
+
 # Here we are compiling the space selectors with the relevant optimization flag.
 add_library(VectorSimilaritySpaces
 	L2_space.cpp
@@ -190,4 +401,16 @@ add_library(VectorSimilaritySpaces
 	computer/preprocessor_container.cpp
 )
 
-target_link_libraries(VectorSimilaritySpaces VectorSimilaritySpaces_no_optimization cpu_features)
+target_link_libraries(VectorSimilaritySpaces VectorSimilaritySpaces_no_optimization cpu_features
+	vecsim_spaces_manifest)
+
+if(NOT SPACES_BASELINE_ARCH_FLAG STREQUAL "")
+	# Appended at target level (PRIVATE, so it does not propagate to consumers linking this
+	# library) rather than folded into CMAKE_CXX_FLAGS, so it overrides anything a parent build
+	# inherited through CMAKE_CXX_FLAGS. CMake emits target-level COMPILE_OPTIONS before
+	# source-level COMPILE_FLAGS on the same command line, so the per-tier ISA flags attached
+	# above via set_source_files_properties() still win for the functions/*.cpp TUs that carry
+	# them.
+	target_compile_options(VectorSimilaritySpaces_no_optimization PRIVATE ${SPACES_BASELINE_ARCH_FLAG})
+	target_compile_options(VectorSimilaritySpaces PRIVATE ${SPACES_BASELINE_ARCH_FLAG})
+endif()
diff --git a/src/VecSim/spaces/IP/IP_AVX512FP16_VL_FP16.h b/src/VecSim/spaces/IP/IP_AVX512FP16_VL_FP16.h
index 130ff2c7a..9e53092ce 100644
--- a/src/VecSim/spaces/IP/IP_AVX512FP16_VL_FP16.h
+++ b/src/VecSim/spaces/IP/IP_AVX512FP16_VL_FP16.h
@@ -6,6 +6,7 @@
  * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
  * GNU Affero General Public License v3 (AGPLv3).
  */
+#pragma once
 #include <cstdint>
 #include "VecSim/spaces/space_includes.h"
 #include "VecSim/types/float16.h"
@@ -13,13 +14,17 @@
 
 using float16 = vecsim_types::float16;
 
-static void InnerProductStep(float16 *&pVect1, float16 *&pVect2, __m512h &sum) {
-    __m512h v1 = _mm512_loadu_ph(pVect1);
-    __m512h v2 = _mm512_loadu_ph(pVect2);
-
-    sum = _mm512_fmadd_ph(v1, v2, sum);
-    pVect1 += 32;
-    pVect2 += 32;
+// See the note in L2_AVX512FP16_VL_FP16.h: the products accumulate in fp32, matching
+// `FP16_InnerProduct` and mirroring IP_AVX512F_FP16.h, because a half precision accumulator both
+// loses precision on every add and overflows to infinity past 65504, the largest finite fp16 value.
+static void InnerProductStep(float16 *&pVect1, float16 *&pVect2, __m512 &sum) {
+    // Convert 16 half-floats into floats and store them in 512 bits register.
+    auto v1 = _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect1));
+    auto v2 = _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect2));
+
+    sum = _mm512_fmadd_ps(v1, v2, sum);
+    pVect1 += 16;
+    pVect2 += 16;
 }
 
 template <unsigned short residual> // 0..31
@@ -30,22 +35,29 @@ float FP16_InnerProductSIMD32_AVX512FP16_VL(const void *pVect1v, const void *pVe
 
     const float16 *pEnd1 = pVect1 + dimension;
 
-    __m512h sum = _mm512_setzero_ph();
-
-    if constexpr (residual) {
-        constexpr __mmask32 mask = (1LU << residual) - 1;
-        __m512h v1 = _mm512_loadu_ph(pVect1);
-        pVect1 += residual;
-        __m512h v2 = _mm512_loadu_ph(pVect2);
-        pVect2 += residual;
-        sum = _mm512_maskz_mul_ph(mask, v1, v2);
+    // Two accumulators break the FMA dependency chain, letting more FMAs be in flight at once.
+    auto sum0 = _mm512_setzero_ps();
+    auto sum1 = _mm512_setzero_ps();
+
+    if constexpr (residual % 16) {
+        __mmask16 constexpr residuals_mask = (1 << (residual % 16)) - 1;
+        auto v1 = _mm512_maskz_mov_ps(residuals_mask,
+                                      _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect1)));
+        auto v2 = _mm512_maskz_mov_ps(residuals_mask,
+                                      _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect2)));
+        sum0 = _mm512_mul_ps(v1, v2);
+        pVect1 += residual % 16;
+        pVect2 += residual % 16;
+    }
+    if constexpr (residual >= 16) {
+        InnerProductStep(pVect1, pVect2, sum1);
     }
 
     // We dealt with the residual part. We are left with some multiple of 32 16-bit floats.
-    do {
-        InnerProductStep(pVect1, pVect2, sum);
-    } while (pVect1 < pEnd1);
+    while (pVect1 < pEnd1) {
+        InnerProductStep(pVect1, pVect2, sum0);
+        InnerProductStep(pVect1, pVect2, sum1);
+    }
 
-    _Float16 res = _mm512_reduce_add_ph(sum);
-    return _Float16(1) - res;
+    return 1.0f - _mm512_reduce_add_ps(_mm512_add_ps(sum0, sum1));
 }
diff --git a/src/VecSim/spaces/IP/IP_NEON_FP16.h b/src/VecSim/spaces/IP/IP_NEON_FP16.h
index fd547c457..93f9f06e0 100644
--- a/src/VecSim/spaces/IP/IP_NEON_FP16.h
+++ b/src/VecSim/spaces/IP/IP_NEON_FP16.h
@@ -6,17 +6,26 @@
  * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
  * GNU Affero General Public License v3 (AGPLv3).
  */
+#pragma once
 #include <arm_neon.h>
 
-inline void InnerProduct_Step(const float16_t *&vec1, const float16_t *&vec2, float16x8_t &acc) {
+// The products accumulate in fp32, not fp16. `FP16_InnerProduct` widens each stored half with
+// FP16_to_FP32 and accumulates into a float, so a half precision accumulator would make this tier
+// disagree with the same function computed anywhere else. It is also unsafe: 65504 is the largest
+// finite fp16 value, so 32 elements of 200.0, all ordinary fp16 values, drive a half precision
+// accumulator past it and the result becomes infinity. An fp32 accumulator cannot overflow for
+// any fp16 input.
+inline void InnerProduct_Step(const float16_t *&vec1, const float16_t *&vec2, float32x4_t &acc_lo,
+                              float32x4_t &acc_hi) {
     // Load half-precision vectors
     float16x8_t v1 = vld1q_f16(vec1);
     float16x8_t v2 = vld1q_f16(vec2);
     vec1 += 8;
     vec2 += 8;
 
-    // Multiply and accumulate
-    acc = vfmaq_f16(acc, v1, v2);
+    // Widen both halves to single precision, then multiply and accumulate in fp32.
+    acc_lo = vfmaq_f32(acc_lo, vcvt_f32_f16(vget_low_f16(v1)), vcvt_f32_f16(vget_low_f16(v2)));
+    acc_hi = vfmaq_f32(acc_hi, vcvt_high_f32_f16(v1), vcvt_high_f32_f16(v2));
 }
 
 template <unsigned char residual> // 0..31
@@ -24,10 +33,11 @@ float FP16_InnerProduct_NEON_HP(const void *pVect1v, const void *pVect2v, size_t
     const auto *vec1 = static_cast<const float16_t *>(pVect1v);
     const auto *vec2 = static_cast<const float16_t *>(pVect2v);
     const auto *const v1End = vec1 + dimension;
-    float16x8_t acc1 = vdupq_n_f16(0.0f);
-    float16x8_t acc2 = vdupq_n_f16(0.0f);
-    float16x8_t acc3 = vdupq_n_f16(0.0f);
-    float16x8_t acc4 = vdupq_n_f16(0.0f);
+    // Four accumulator pairs, keeping the original four-way unrolling with fp32 accumulators.
+    float32x4_t acc1_lo = vdupq_n_f32(0.0f), acc1_hi = vdupq_n_f32(0.0f);
+    float32x4_t acc2_lo = vdupq_n_f32(0.0f), acc2_hi = vdupq_n_f32(0.0f);
+    float32x4_t acc3_lo = vdupq_n_f32(0.0f), acc3_hi = vdupq_n_f32(0.0f);
+    float32x4_t acc4_lo = vdupq_n_f32(0.0f), acc4_hi = vdupq_n_f32(0.0f);
 
     // First, handle the partial chunk residual
     if constexpr (residual % 8) {
@@ -48,12 +58,15 @@ float FP16_InnerProduct_NEON_HP(const void *pVect1v, const void *pVect2v, size_t
         float16x8_t v1 = vld1q_f16(vec1);
         float16x8_t v2 = vld1q_f16(vec2);
 
-        // Apply mask to both vectors
-        float16x8_t masked_v1 = vbslq_f16(mask, v1, acc1); // `acc1` should be all zeros here
-        float16x8_t masked_v2 = vbslq_f16(mask, v2, acc2); // `acc2` should be all zeros here
+        // Apply mask to both vectors, zeroing the lanes past the residual.
+        const float16x8_t zero_h = vdupq_n_f16(0.0f);
+        float16x8_t masked_v1 = vbslq_f16(mask, v1, zero_h);
+        float16x8_t masked_v2 = vbslq_f16(mask, v2, zero_h);
 
-        // Multiply and accumulate
-        acc1 = vfmaq_f16(acc1, masked_v1, masked_v2);
+        // Multiply and accumulate in fp32; the masked lanes contribute zero.
+        acc1_lo = vfmaq_f32(acc1_lo, vcvt_f32_f16(vget_low_f16(masked_v1)),
+                            vcvt_f32_f16(vget_low_f16(masked_v2)));
+        acc1_hi = vfmaq_f32(acc1_hi, vcvt_high_f32_f16(masked_v1), vcvt_high_f32_f16(masked_v2));
 
         // Advance pointers
         vec1 += chunk_residual;
@@ -62,34 +75,26 @@ float FP16_InnerProduct_NEON_HP(const void *pVect1v, const void *pVect2v, size_t
 
     // Handle (residual - (residual % 8)) in chunks of 8 float16
     if constexpr (residual >= 8)
-        InnerProduct_Step(vec1, vec2, acc2);
+        InnerProduct_Step(vec1, vec2, acc2_lo, acc2_hi);
     if constexpr (residual >= 16)
-        InnerProduct_Step(vec1, vec2, acc3);
+        InnerProduct_Step(vec1, vec2, acc3_lo, acc3_hi);
     if constexpr (residual >= 24)
-        InnerProduct_Step(vec1, vec2, acc4);
+        InnerProduct_Step(vec1, vec2, acc4_lo, acc4_hi);
 
     // Process the rest of the vectors (the full chunks part)
     while (vec1 < v1End) {
         // TODO: use `vld1q_f16_x4` for quad-loading?
-        InnerProduct_Step(vec1, vec2, acc1);
-        InnerProduct_Step(vec1, vec2, acc2);
-        InnerProduct_Step(vec1, vec2, acc3);
-        InnerProduct_Step(vec1, vec2, acc4);
+        InnerProduct_Step(vec1, vec2, acc1_lo, acc1_hi);
+        InnerProduct_Step(vec1, vec2, acc2_lo, acc2_hi);
+        InnerProduct_Step(vec1, vec2, acc3_lo, acc3_hi);
+        InnerProduct_Step(vec1, vec2, acc4_lo, acc4_hi);
     }
 
-    // Accumulate accumulators
-    acc1 = vpaddq_f16(acc1, acc3);
-    acc2 = vpaddq_f16(acc2, acc4);
-    acc1 = vpaddq_f16(acc1, acc2);
-
-    // Horizontal sum of the accumulated values
-    float32x4_t sum_f32 = vcvt_f32_f16(vget_low_f16(acc1));
-    sum_f32 = vaddq_f32(sum_f32, vcvt_f32_f16(vget_high_f16(acc1)));
-
-    // Pairwise add to get horizontal sum
-    float32x2_t sum_2 = vadd_f32(vget_low_f32(sum_f32), vget_high_f32(sum_f32));
-    sum_2 = vpadd_f32(sum_2, sum_2);
+    // Accumulate accumulators, all in fp32.
+    float32x4_t sum_f32 = vaddq_f32(vaddq_f32(acc1_lo, acc1_hi), vaddq_f32(acc2_lo, acc2_hi));
+    sum_f32 = vaddq_f32(sum_f32, vaddq_f32(acc3_lo, acc3_hi));
+    sum_f32 = vaddq_f32(sum_f32, vaddq_f32(acc4_lo, acc4_hi));
 
     // Extract result
-    return 1.0f - vget_lane_f32(sum_2, 0);
+    return 1.0f - vaddvq_f32(sum_f32);
 }
diff --git a/src/VecSim/spaces/IP/IP_SVE_FP16.h b/src/VecSim/spaces/IP/IP_SVE_FP16.h
index ac464977e..ca938bf0a 100644
--- a/src/VecSim/spaces/IP/IP_SVE_FP16.h
+++ b/src/VecSim/spaces/IP/IP_SVE_FP16.h
@@ -6,17 +6,44 @@
  * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
  * GNU Affero General Public License v3 (AGPLv3).
  */
+#pragma once
 #include <arm_sve.h>
 
-inline void InnerProduct_Step(const float16_t *vec1, const float16_t *vec2, svfloat16_t &acc,
-                              size_t &offset, const size_t chunk) {
+// Widen a half-precision vector into two single-precision vectors. `svcvt_f32_f16` reads each
+// input from the bottom 16 bits of a 32-bit lane, and ZIP1/ZIP2 interleave the lower and upper
+// halves of their operands, so zipping against zero leaves `lo` holding the vector's lower
+// contiguous half (elements 0 .. N/2-1) and `hi` the upper half, one value per 32-bit lane.
+// Splitting this way changes the summation order relative to a scalar loop, and fp32 addition still
+// rounds, so the result can differ in the last bits. That is true of every accumulator split in
+// these kernels, which is why the randomized tests compare against a tolerance.
+inline void widen_f16_to_f32(svfloat16_t v, svfloat32_t &lo, svfloat32_t &hi) {
+    const svfloat16_t zero = svdup_f16(0.0f);
+    lo = svcvt_f32_f16_x(svptrue_b32(), svzip1_f16(v, zero));
+    hi = svcvt_f32_f16_x(svptrue_b32(), svzip2_f16(v, zero));
+}
+
+// The products accumulate in fp32, not fp16. `FP16_InnerProduct` widens each stored half with
+// FP16_to_FP32 and accumulates into a float, so a half precision accumulator would make this tier
+// disagree with the same function computed anywhere else. It is also unsafe: 65504 is the largest
+// finite fp16 value, so 32 elements of 200.0, all ordinary fp16 values, drive a half precision
+// accumulator past it and the result becomes infinity. An fp32 accumulator cannot overflow for
+// any fp16 input.
+inline void InnerProduct_Step(const float16_t *vec1, const float16_t *vec2, svfloat32_t &acc_lo,
+                              svfloat32_t &acc_hi, size_t &offset, const size_t chunk) {
     svbool_t all = svptrue_b16();
+    svbool_t all32 = svptrue_b32();
 
     // Load half-precision vectors.
     svfloat16_t v1 = svld1_f16(all, vec1 + offset);
     svfloat16_t v2 = svld1_f16(all, vec2 + offset);
-    // Compute multiplications and add to the accumulator
-    acc = svmla_f16_x(all, acc, v1, v2);
+
+    svfloat32_t a_lo, a_hi, b_lo, b_hi;
+    widen_f16_to_f32(v1, a_lo, a_hi);
+    widen_f16_to_f32(v2, b_lo, b_hi);
+
+    // Compute multiplications and add to the accumulators, in single precision.
+    acc_lo = svmla_f32_x(all32, acc_lo, a_lo, b_lo);
+    acc_hi = svmla_f32_x(all32, acc_hi, a_hi, b_hi);
 
     // Move to next chunk
     offset += chunk;
@@ -27,48 +54,55 @@ float FP16_InnerProduct_SVE(const void *pVect1v, const void *pVect2v, size_t dim
     const auto *vec1 = static_cast<const float16_t *>(pVect1v);
     const auto *vec2 = static_cast<const float16_t *>(pVect2v);
     const size_t chunk = svcnth(); // number of 16-bit elements in a register
-    svbool_t all = svptrue_b16();
-    svfloat16_t acc1 = svdup_f16(0.0f);
-    svfloat16_t acc2 = svdup_f16(0.0f);
-    svfloat16_t acc3 = svdup_f16(0.0f);
-    svfloat16_t acc4 = svdup_f16(0.0f);
+    // Four accumulator pairs, keeping the original four-way unrolling with fp32 accumulators.
+    svfloat32_t acc1_lo = svdup_f32(0.0f), acc1_hi = svdup_f32(0.0f);
+    svfloat32_t acc2_lo = svdup_f32(0.0f), acc2_hi = svdup_f32(0.0f);
+    svfloat32_t acc3_lo = svdup_f32(0.0f), acc3_hi = svdup_f32(0.0f);
+    svfloat32_t acc4_lo = svdup_f32(0.0f), acc4_hi = svdup_f32(0.0f);
     size_t offset = 0;
 
     // Process all full vectors
     const size_t full_iterations = dimension / chunk / 4;
     for (size_t iter = 0; iter < full_iterations; iter++) {
-        InnerProduct_Step(vec1, vec2, acc1, offset, chunk);
-        InnerProduct_Step(vec1, vec2, acc2, offset, chunk);
-        InnerProduct_Step(vec1, vec2, acc3, offset, chunk);
-        InnerProduct_Step(vec1, vec2, acc4, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc1_lo, acc1_hi, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc2_lo, acc2_hi, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc3_lo, acc3_hi, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc4_lo, acc4_hi, offset, chunk);
     }
 
     // Perform between 0 and 3 additional steps, according to `additional_steps` value
     if constexpr (additional_steps >= 1)
-        InnerProduct_Step(vec1, vec2, acc1, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc1_lo, acc1_hi, offset, chunk);
     if constexpr (additional_steps >= 2)
-        InnerProduct_Step(vec1, vec2, acc2, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc2_lo, acc2_hi, offset, chunk);
     if constexpr (additional_steps >= 3)
-        InnerProduct_Step(vec1, vec2, acc3, offset, chunk);
+        InnerProduct_Step(vec1, vec2, acc3_lo, acc3_hi, offset, chunk);
 
     // Handle the tail with the residual predicate
     if constexpr (partial_chunk) {
         svbool_t pg = svwhilelt_b16_u64(offset, dimension);
 
-        // Load half-precision vectors.
+        // The predicated load zeroes the inactive lanes, so the arithmetic below can run
+        // unpredicated: those lanes contribute a zero product.
         svfloat16_t v1 = svld1_f16(pg, vec1 + offset);
         svfloat16_t v2 = svld1_f16(pg, vec2 + offset);
-        // Compute multiplications and add to the accumulator.
-        // use the existing value of `acc` for the inactive elements (by the `m` suffix)
-        acc4 = svmla_f16_m(pg, acc4, v1, v2);
+
+        svfloat32_t a_lo, a_hi, b_lo, b_hi;
+        widen_f16_to_f32(v1, a_lo, a_hi);
+        widen_f16_to_f32(v2, b_lo, b_hi);
+
+        svbool_t all32 = svptrue_b32();
+        acc4_lo = svmla_f32_x(all32, acc4_lo, a_lo, b_lo);
+        acc4_hi = svmla_f32_x(all32, acc4_hi, a_hi, b_hi);
     }
 
-    // Accumulate accumulators
-    acc1 = svadd_f16_x(all, acc1, acc3);
-    acc2 = svadd_f16_x(all, acc2, acc4);
-    acc1 = svadd_f16_x(all, acc1, acc2);
+    // Accumulate accumulators, all in fp32.
+    svbool_t all32 = svptrue_b32();
+    svfloat32_t sum = svadd_f32_x(all32, svadd_f32_x(all32, acc1_lo, acc1_hi),
+                                  svadd_f32_x(all32, acc2_lo, acc2_hi));
+    sum = svadd_f32_x(all32, sum, svadd_f32_x(all32, acc3_lo, acc3_hi));
+    sum = svadd_f32_x(all32, sum, svadd_f32_x(all32, acc4_lo, acc4_hi));
 
     // Reduce the accumulated sum.
-    float result = svaddv_f16(all, acc1);
-    return 1.0f - result;
+    return 1.0f - svaddv_f32(all32, sum);
 }
diff --git a/src/VecSim/spaces/IP_space.cpp b/src/VecSim/spaces/IP_space.cpp
index b7f963d2c..d13cc1fc2 100644
--- a/src/VecSim/spaces/IP_space.cpp
+++ b/src/VecSim/spaces/IP_space.cpp
@@ -77,7 +77,7 @@ dist_func_t<float> IP_SQ8_FP32_GetDistFunc(size_t dim, unsigned char *alignment,
     }
     // Alignment hints below refer to the SQ8 (first) operand per the GetDistFunc contract.
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (features.avx512f && features.avx512bw && features.avx512vnni) {
+    if (features.avx512f && features.avx512bw && features.avx512vl && features.avx512vnni) {
         if (dim % 16 == 0) // SQ8 chunk = 16 bytes
             *alignment = 16 * sizeof(uint8_t);
         return Choose_SQ8_FP32_IP_implementation_AVX512F_BW_VL_VNNI(dim);
@@ -146,7 +146,7 @@ dist_func_t<float> Cosine_SQ8_FP32_GetDistFunc(size_t dim, unsigned char *alignm
     }
     // Alignment hints below refer to the SQ8 (first) operand per the GetDistFunc contract.
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (features.avx512f && features.avx512bw && features.avx512vnni) {
+    if (features.avx512f && features.avx512bw && features.avx512vl && features.avx512vnni) {
         if (dim % 16 == 0) // SQ8 chunk = 16 bytes
             *alignment = 16 * sizeof(uint8_t);
         return Choose_SQ8_FP32_Cosine_implementation_AVX512F_BW_VL_VNNI(dim);
@@ -375,7 +375,8 @@ dist_func_t<float> IP_SQ8_SQ8_GetDistFunc(size_t dim, unsigned char *alignment,
 #ifdef CPU_FEATURES_ARCH_X86_64
 #ifdef OPT_AVX512_F_BW_VL_VNNI
     // AVX512 VNNI SQ8_SQ8 uses 64-element chunks; residual handling is in 32-byte sub-chunks.
-    if (dim >= 64 && features.avx512f && features.avx512bw && features.avx512vnni) {
+    if (dim >= 64 && features.avx512f && features.avx512bw && features.avx512vl &&
+        features.avx512vnni) {
         if (dim % 32 == 0) // align to 256 bits when there is no offsetting residual
             *alignment = 32 * sizeof(uint8_t);
         return Choose_SQ8_SQ8_IP_implementation_AVX512F_BW_VL_VNNI(dim);
@@ -427,7 +428,8 @@ dist_func_t<float> Cosine_SQ8_SQ8_GetDistFunc(size_t dim, unsigned char *alignme
 #ifdef CPU_FEATURES_ARCH_X86_64
 #ifdef OPT_AVX512_F_BW_VL_VNNI
     // AVX512 VNNI SQ8_SQ8 uses 64-element chunks; residual handling is in 32-byte sub-chunks.
-    if (dim >= 64 && features.avx512f && features.avx512bw && features.avx512vnni) {
+    if (dim >= 64 && features.avx512f && features.avx512bw && features.avx512vl &&
+        features.avx512vnni) {
         if (dim % 32 == 0) // align to 256 bits when there is no offsetting residual
             *alignment = 32 * sizeof(uint8_t);
         return Choose_SQ8_SQ8_Cosine_implementation_AVX512F_BW_VL_VNNI(dim);
diff --git a/src/VecSim/spaces/L2/L2_AVX512FP16_VL_FP16.h b/src/VecSim/spaces/L2/L2_AVX512FP16_VL_FP16.h
index 27e909a30..d4d59d33d 100644
--- a/src/VecSim/spaces/L2/L2_AVX512FP16_VL_FP16.h
+++ b/src/VecSim/spaces/L2/L2_AVX512FP16_VL_FP16.h
@@ -6,6 +6,7 @@
  * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
  * GNU Affero General Public License v3 (AGPLv3).
  */
+#pragma once
 #include <cstdint>
 #include "VecSim/spaces/space_includes.h"
 #include "VecSim/types/float16.h"
@@ -13,15 +14,23 @@
 
 using float16 = vecsim_types::float16;
 
-static inline void L2SqrStep(float16 *&pVect1, float16 *&pVect2, __m512h &sum) {
-    __m512h v1 = _mm512_loadu_ph(pVect1);
-    __m512h v2 = _mm512_loadu_ph(pVect2);
+// The arithmetic here is fp32, not fp16. `FP16_L2Sqr` widens each stored half with FP16_to_FP32 and
+// accumulates into a float, so accumulating in half precision would make this tier disagree with
+// the same function computed anywhere else. It is also unsafe: 65504 is the largest finite fp16
+// value, so 32 elements of 200.0, all ordinary fp16 values, drive a half precision accumulator
+// past it and the result becomes infinity. An fp32 accumulator cannot overflow for any fp16 input.
+// This mirrors L2_AVX512F_FP16.h step for step; after widening there is nothing
+// half-precision-specific left to do differently.
+static inline void L2SqrStep(float16 *&pVect1, float16 *&pVect2, __m512 &sum) {
+    // Convert 16 half-floats into floats and store them in 512 bits register.
+    auto v1 = _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect1));
+    auto v2 = _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect2));
 
-    __m512h diff = _mm512_sub_ph(v1, v2);
-
-    sum = _mm512_fmadd_ph(diff, diff, sum);
-    pVect1 += 32;
-    pVect2 += 32;
+    // sum = (v1 - v2)^2 + sum
+    auto c = _mm512_sub_ps(v1, v2);
+    sum = _mm512_fmadd_ps(c, c, sum);
+    pVect1 += 16;
+    pVect2 += 16;
 }
 
 template <unsigned short residual> // 0..31
@@ -31,24 +40,33 @@ float FP16_L2SqrSIMD32_AVX512FP16_VL(const void *pVect1v, const void *pVect2v, s
 
     const float16 *pEnd1 = pVect1 + dimension;
 
-    __m512h sum = _mm512_setzero_ph();
-
-    if constexpr (residual) {
-        constexpr __mmask32 mask = (1LU << residual) - 1;
-        __m512h v1 = _mm512_loadu_ph(pVect1);
-        pVect1 += residual;
-        __m512h v2 = _mm512_loadu_ph(pVect2);
-        pVect2 += residual;
-        __m512h diff = _mm512_maskz_sub_ph(mask, v1, v2);
+    // Two accumulators break the FMA dependency chain, letting more FMAs be in flight at once.
+    auto sum0 = _mm512_setzero_ps();
+    auto sum1 = _mm512_setzero_ps();
 
-        sum = _mm512_mul_ph(diff, diff);
+    if constexpr (residual % 16) {
+        // Deal with remainder first. The full-width load of 16 16-bit floats is safe because
+        // `dim` is at least 16, so the vector spans at least 16 elements.
+        __mmask16 constexpr residuals_mask = (1 << (residual % 16)) - 1;
+        auto v1 = _mm512_maskz_mov_ps(residuals_mask,
+                                      _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect1)));
+        auto v2 = _mm512_maskz_mov_ps(residuals_mask,
+                                      _mm512_cvtph_ps(_mm256_lddqu_si256((__m256i *)pVect2)));
+        auto c = _mm512_sub_ps(v1, v2);
+        sum0 = _mm512_mul_ps(c, c);
+        pVect1 += residual % 16;
+        pVect2 += residual % 16;
+    }
+    // Handle the remaining full 16-element block of the residual (compile-time resolved).
+    if constexpr (residual >= 16) {
+        L2SqrStep(pVect1, pVect2, sum1);
     }
 
     // We dealt with the residual part. We are left with some multiple of 32 16-bit floats.
-    do {
-        L2SqrStep(pVect1, pVect2, sum);
-    } while (pVect1 < pEnd1);
+    while (pVect1 < pEnd1) {
+        L2SqrStep(pVect1, pVect2, sum0);
+        L2SqrStep(pVect1, pVect2, sum1);
+    }
 
-    _Float16 res = _mm512_reduce_add_ph(sum);
-    return res;
+    return _mm512_reduce_add_ps(_mm512_add_ps(sum0, sum1));
 }
diff --git a/src/VecSim/spaces/L2/L2_NEON_FP16.h b/src/VecSim/spaces/L2/L2_NEON_FP16.h
index e2786aa7a..52b30e283 100644
--- a/src/VecSim/spaces/L2/L2_NEON_FP16.h
+++ b/src/VecSim/spaces/L2/L2_NEON_FP16.h
@@ -6,19 +6,28 @@
  * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
  * GNU Affero General Public License v3 (AGPLv3).
  */
+#pragma once
 #include <arm_neon.h>
 
-inline void L2Sqr_Step(const float16_t *&vec1, const float16_t *&vec2, float16x8_t &acc) {
+// The squared differences accumulate in fp32, not fp16. `FP16_L2Sqr` widens each stored half with
+// FP16_to_FP32, subtracts in float and accumulates into a float, so a half precision accumulator
+// would make this tier disagree with the same function computed anywhere else. It is also unsafe:
+// 65504 is the largest finite fp16 value, so 32 elements of 200.0, all ordinary fp16 values, drive
+// a half precision accumulator past it and the result becomes infinity. An fp32 accumulator cannot
+// overflow for any fp16 input.
+inline void L2Sqr_Step(const float16_t *&vec1, const float16_t *&vec2, float32x4_t &acc_lo,
+                       float32x4_t &acc_hi) {
     // Load half-precision vectors
     float16x8_t v1 = vld1q_f16(vec1);
     float16x8_t v2 = vld1q_f16(vec2);
     vec1 += 8;
     vec2 += 8;
 
-    // Calculate differences
-    float16x8_t diff = vsubq_f16(v1, v2);
-    // Square and accumulate
-    acc = vfmaq_f16(acc, diff, diff);
+    // Widen both halves to single precision, then subtract and accumulate in fp32.
+    float32x4_t d_lo = vsubq_f32(vcvt_f32_f16(vget_low_f16(v1)), vcvt_f32_f16(vget_low_f16(v2)));
+    float32x4_t d_hi = vsubq_f32(vcvt_high_f32_f16(v1), vcvt_high_f32_f16(v2));
+    acc_lo = vfmaq_f32(acc_lo, d_lo, d_lo);
+    acc_hi = vfmaq_f32(acc_hi, d_hi, d_hi);
 }
 
 template <unsigned char residual> // 0..31
@@ -26,10 +35,11 @@ float FP16_L2Sqr_NEON_HP(const void *pVect1v, const void *pVect2v, size_t dimens
     const auto *vec1 = static_cast<const float16_t *>(pVect1v);
     const auto *vec2 = static_cast<const float16_t *>(pVect2v);
     const auto *const v1End = vec1 + dimension;
-    float16x8_t acc1 = vdupq_n_f16(0.0f);
-    float16x8_t acc2 = vdupq_n_f16(0.0f);
-    float16x8_t acc3 = vdupq_n_f16(0.0f);
-    float16x8_t acc4 = vdupq_n_f16(0.0f);
+    // Four accumulator pairs, keeping the original four-way unrolling with fp32 accumulators.
+    float32x4_t acc1_lo = vdupq_n_f32(0.0f), acc1_hi = vdupq_n_f32(0.0f);
+    float32x4_t acc2_lo = vdupq_n_f32(0.0f), acc2_hi = vdupq_n_f32(0.0f);
+    float32x4_t acc3_lo = vdupq_n_f32(0.0f), acc3_hi = vdupq_n_f32(0.0f);
+    float32x4_t acc4_lo = vdupq_n_f32(0.0f), acc4_hi = vdupq_n_f32(0.0f);
 
     // First, handle the partial chunk residual
     if constexpr (residual % 8) {
@@ -51,13 +61,16 @@ float FP16_L2Sqr_NEON_HP(const void *pVect1v, const void *pVect2v, size_t dimens
         float16x8_t v2 = vld1q_f16(vec2);
 
         // Apply mask to both vectors
-        float16x8_t masked_v1 = vbslq_f16(mask, v1, acc1); // `acc1` should be all zeros here
-        float16x8_t masked_v2 = vbslq_f16(mask, v2, acc2); // `acc2` should be all zeros here
+        const float16x8_t zero_h = vdupq_n_f16(0.0f);
+        float16x8_t masked_v1 = vbslq_f16(mask, v1, zero_h);
+        float16x8_t masked_v2 = vbslq_f16(mask, v2, zero_h);
 
-        // Calculate differences
-        float16x8_t diff = vsubq_f16(masked_v1, masked_v2);
-        // Square and accumulate
-        acc1 = vfmaq_f16(acc1, diff, diff);
+        // Widen, subtract and accumulate in fp32; the masked lanes contribute zero.
+        float32x4_t d_lo =
+            vsubq_f32(vcvt_f32_f16(vget_low_f16(masked_v1)), vcvt_f32_f16(vget_low_f16(masked_v2)));
+        float32x4_t d_hi = vsubq_f32(vcvt_high_f32_f16(masked_v1), vcvt_high_f32_f16(masked_v2));
+        acc1_lo = vfmaq_f32(acc1_lo, d_lo, d_lo);
+        acc1_hi = vfmaq_f32(acc1_hi, d_hi, d_hi);
 
         // Advance pointers
         vec1 += chunk_residual;
@@ -66,34 +79,26 @@ float FP16_L2Sqr_NEON_HP(const void *pVect1v, const void *pVect2v, size_t dimens
 
     // Handle (residual - (residual % 8)) in chunks of 8 float16
     if constexpr (residual >= 8)
-        L2Sqr_Step(vec1, vec2, acc2);
+        L2Sqr_Step(vec1, vec2, acc2_lo, acc2_hi);
     if constexpr (residual >= 16)
-        L2Sqr_Step(vec1, vec2, acc3);
+        L2Sqr_Step(vec1, vec2, acc3_lo, acc3_hi);
     if constexpr (residual >= 24)
-        L2Sqr_Step(vec1, vec2, acc4);
+        L2Sqr_Step(vec1, vec2, acc4_lo, acc4_hi);
 
     // Process the rest of the vectors (the full chunks part)
     while (vec1 < v1End) {
         // TODO: use `vld1q_f16_x4` for quad-loading?
-        L2Sqr_Step(vec1, vec2, acc1);
-        L2Sqr_Step(vec1, vec2, acc2);
-        L2Sqr_Step(vec1, vec2, acc3);
-        L2Sqr_Step(vec1, vec2, acc4);
+        L2Sqr_Step(vec1, vec2, acc1_lo, acc1_hi);
+        L2Sqr_Step(vec1, vec2, acc2_lo, acc2_hi);
+        L2Sqr_Step(vec1, vec2, acc3_lo, acc3_hi);
+        L2Sqr_Step(vec1, vec2, acc4_lo, acc4_hi);
     }
 
-    // Accumulate accumulators
-    acc1 = vpaddq_f16(acc1, acc3);
-    acc2 = vpaddq_f16(acc2, acc4);
-    acc1 = vpaddq_f16(acc1, acc2);
-
-    // Horizontal sum of the accumulated values
-    float32x4_t sum_f32 = vcvt_f32_f16(vget_low_f16(acc1));
-    sum_f32 = vaddq_f32(sum_f32, vcvt_f32_f16(vget_high_f16(acc1)));
-
-    // Pairwise add to get horizontal sum
-    float32x2_t sum_2 = vadd_f32(vget_low_f32(sum_f32), vget_high_f32(sum_f32));
-    sum_2 = vpadd_f32(sum_2, sum_2);
+    // Accumulate accumulators, all in fp32.
+    float32x4_t sum_f32 = vaddq_f32(vaddq_f32(acc1_lo, acc1_hi), vaddq_f32(acc2_lo, acc2_hi));
+    sum_f32 = vaddq_f32(sum_f32, vaddq_f32(acc3_lo, acc3_hi));
+    sum_f32 = vaddq_f32(sum_f32, vaddq_f32(acc4_lo, acc4_hi));
 
     // Extract result
-    return vget_lane_f32(sum_2, 0);
+    return vaddvq_f32(sum_f32);
 }
diff --git a/src/VecSim/spaces/L2/L2_SVE_FP16.h b/src/VecSim/spaces/L2/L2_SVE_FP16.h
index 24b5ee2df..f0d6a7d8d 100644
--- a/src/VecSim/spaces/L2/L2_SVE_FP16.h
+++ b/src/VecSim/spaces/L2/L2_SVE_FP16.h
@@ -6,18 +6,34 @@
  * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
  * GNU Affero General Public License v3 (AGPLv3).
  */
+#pragma once
 #include <arm_sve.h>
+// widen_f16_to_f32 lives here: SVE.cpp compiles both headers, so it must be defined once.
+#include "VecSim/spaces/IP/IP_SVE_FP16.h"
 
-inline void L2Sqr_Step(const float16_t *vec1, const float16_t *vec2, svfloat16_t &acc,
-                       size_t &offset, const size_t chunk) {
+// The squared differences accumulate in fp32, not fp16. `FP16_L2Sqr` widens each stored half with
+// FP16_to_FP32, subtracts in float and accumulates into a float, so a half precision accumulator
+// would make this tier disagree with the same function computed anywhere else. It is also unsafe:
+// 65504 is the largest finite fp16 value, so 32 elements of 200.0, all ordinary fp16 values, drive
+// a half precision accumulator past it and the result becomes infinity. An fp32 accumulator cannot
+// overflow for any fp16 input.
+inline void L2Sqr_Step(const float16_t *vec1, const float16_t *vec2, svfloat32_t &acc_lo,
+                       svfloat32_t &acc_hi, size_t &offset, const size_t chunk) {
     svbool_t all = svptrue_b16();
+    svbool_t all32 = svptrue_b32();
 
     svfloat16_t v1 = svld1_f16(all, vec1 + offset);
     svfloat16_t v2 = svld1_f16(all, vec2 + offset);
-    // Compute difference in half precision.
-    svfloat16_t diff = svsub_f16_x(all, v1, v2);
-    // Square the differences and accumulate
-    acc = svmla_f16_x(all, acc, diff, diff);
+
+    svfloat32_t a_lo, a_hi, b_lo, b_hi;
+    widen_f16_to_f32(v1, a_lo, a_hi);
+    widen_f16_to_f32(v2, b_lo, b_hi);
+
+    // Subtract and accumulate in single precision.
+    svfloat32_t d_lo = svsub_f32_x(all32, a_lo, b_lo);
+    svfloat32_t d_hi = svsub_f32_x(all32, a_hi, b_hi);
+    acc_lo = svmla_f32_x(all32, acc_lo, d_lo, d_lo);
+    acc_hi = svmla_f32_x(all32, acc_hi, d_hi, d_hi);
     offset += chunk;
 }
 
@@ -26,50 +42,57 @@ float FP16_L2Sqr_SVE(const void *pVect1v, const void *pVect2v, size_t dimension)
     const auto *vec1 = static_cast<const float16_t *>(pVect1v);
     const auto *vec2 = static_cast<const float16_t *>(pVect2v);
     const size_t chunk = svcnth(); // number of 16-bit elements in a register
-    svbool_t all = svptrue_b16();
-    svfloat16_t acc1 = svdup_f16(0.0f);
-    svfloat16_t acc2 = svdup_f16(0.0f);
-    svfloat16_t acc3 = svdup_f16(0.0f);
-    svfloat16_t acc4 = svdup_f16(0.0f);
+    // Four accumulator pairs, keeping the original four-way unrolling with fp32 accumulators.
+    svfloat32_t acc1_lo = svdup_f32(0.0f), acc1_hi = svdup_f32(0.0f);
+    svfloat32_t acc2_lo = svdup_f32(0.0f), acc2_hi = svdup_f32(0.0f);
+    svfloat32_t acc3_lo = svdup_f32(0.0f), acc3_hi = svdup_f32(0.0f);
+    svfloat32_t acc4_lo = svdup_f32(0.0f), acc4_hi = svdup_f32(0.0f);
     size_t offset = 0;
 
     // Process all full vectors
     const size_t full_iterations = dimension / chunk / 4;
     for (size_t iter = 0; iter < full_iterations; iter++) {
-        L2Sqr_Step(vec1, vec2, acc1, offset, chunk);
-        L2Sqr_Step(vec1, vec2, acc2, offset, chunk);
-        L2Sqr_Step(vec1, vec2, acc3, offset, chunk);
-        L2Sqr_Step(vec1, vec2, acc4, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc1_lo, acc1_hi, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc2_lo, acc2_hi, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc3_lo, acc3_hi, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc4_lo, acc4_hi, offset, chunk);
     }
 
     // Perform between 0 and 3 additional steps, according to `additional_steps` value
     if constexpr (additional_steps >= 1)
-        L2Sqr_Step(vec1, vec2, acc1, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc1_lo, acc1_hi, offset, chunk);
     if constexpr (additional_steps >= 2)
-        L2Sqr_Step(vec1, vec2, acc2, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc2_lo, acc2_hi, offset, chunk);
     if constexpr (additional_steps >= 3)
-        L2Sqr_Step(vec1, vec2, acc3, offset, chunk);
+        L2Sqr_Step(vec1, vec2, acc3_lo, acc3_hi, offset, chunk);
 
     // Handle partial chunk, if needed
     if constexpr (partial_chunk) {
         svbool_t pg = svwhilelt_b16_u64(offset, dimension);
 
-        // Load half-precision vectors.
+        // Load half-precision vectors. The predicated load zeroes the inactive lanes, so the
+        // arithmetic below can run unpredicated: those lanes contribute a squared zero.
         svfloat16_t v1 = svld1_f16(pg, vec1 + offset);
         svfloat16_t v2 = svld1_f16(pg, vec2 + offset);
-        // Compute difference in half precision.
-        svfloat16_t diff = svsub_f16_x(pg, v1, v2);
-        // Square the differences.
-        // Use `m` suffix to keep the inactive elements as they are in `acc`
-        acc4 = svmla_f16_m(pg, acc4, diff, diff);
+
+        svfloat32_t a_lo, a_hi, b_lo, b_hi;
+        widen_f16_to_f32(v1, a_lo, a_hi);
+        widen_f16_to_f32(v2, b_lo, b_hi);
+
+        svbool_t all32 = svptrue_b32();
+        svfloat32_t d_lo = svsub_f32_x(all32, a_lo, b_lo);
+        svfloat32_t d_hi = svsub_f32_x(all32, a_hi, b_hi);
+        acc4_lo = svmla_f32_x(all32, acc4_lo, d_lo, d_lo);
+        acc4_hi = svmla_f32_x(all32, acc4_hi, d_hi, d_hi);
     }
 
-    // Accumulate accumulators
-    acc1 = svadd_f16_x(all, acc1, acc3);
-    acc2 = svadd_f16_x(all, acc2, acc4);
-    acc1 = svadd_f16_x(all, acc1, acc2);
+    // Accumulate accumulators, all in fp32.
+    svbool_t all32 = svptrue_b32();
+    svfloat32_t sum = svadd_f32_x(all32, svadd_f32_x(all32, acc1_lo, acc1_hi),
+                                  svadd_f32_x(all32, acc2_lo, acc2_hi));
+    sum = svadd_f32_x(all32, sum, svadd_f32_x(all32, acc3_lo, acc3_hi));
+    sum = svadd_f32_x(all32, sum, svadd_f32_x(all32, acc4_lo, acc4_hi));
 
     // Reduce the accumulated sum.
-    float result = svaddv_f16(all, acc1);
-    return result;
+    return svaddv_f32(all32, sum);
 }
diff --git a/src/VecSim/spaces/L2_space.cpp b/src/VecSim/spaces/L2_space.cpp
index 2c9223b67..bca916ab3 100644
--- a/src/VecSim/spaces/L2_space.cpp
+++ b/src/VecSim/spaces/L2_space.cpp
@@ -76,7 +76,7 @@ dist_func_t<float> L2_SQ8_FP32_GetDistFunc(size_t dim, unsigned char *alignment,
     }
     // Alignment hints below refer to the SQ8 (first) operand per the GetDistFunc contract.
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (features.avx512f && features.avx512bw && features.avx512vnni) {
+    if (features.avx512f && features.avx512bw && features.avx512vl && features.avx512vnni) {
         if (dim % 16 == 0) // SQ8 chunk = 16 bytes; no point in aligning if there's a residual
             *alignment = 16 * sizeof(uint8_t);
         return Choose_SQ8_FP32_L2_implementation_AVX512F_BW_VL_VNNI(dim);
@@ -563,7 +563,8 @@ dist_func_t<float> L2_SQ8_SQ8_GetDistFunc(size_t dim, unsigned char *alignment,
 #ifdef CPU_FEATURES_ARCH_X86_64
 #ifdef OPT_AVX512_F_BW_VL_VNNI
     // AVX512 VNNI SQ8_SQ8 uses 64-element chunks; residual handling is in 32-byte sub-chunks.
-    if (dim >= 64 && features.avx512f && features.avx512bw && features.avx512vnni) {
+    if (dim >= 64 && features.avx512f && features.avx512bw && features.avx512vl &&
+        features.avx512vnni) {
         if (dim % 32 == 0) // align to 256 bits when there is no offsetting residual
             *alignment = 32 * sizeof(uint8_t);
         return Choose_SQ8_SQ8_L2_implementation_AVX512F_BW_VL_VNNI(dim);
diff --git a/src/VecSim/spaces/functions/AVX2.cpp b/src/VecSim/spaces/functions/AVX2.cpp
index 1a9c41b6f..89db2f768 100644
--- a/src/VecSim/spaces/functions/AVX2.cpp
+++ b/src/VecSim/spaces/functions/AVX2.cpp
@@ -47,6 +47,28 @@ dist_func_t<float> Choose_SQ8_FP32_L2_implementation_AVX2(size_t dim) {
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. These sit inside the region where CHOOSE_IMPLEMENTATION is
+// defined (implementation_chooser.h above, cleanup below) and in the only translation unit compiled
+// with this tier's flags. The kernel headers pull in intrinsics, so none of this may move to a
+// header that a baseline translation unit includes.
+dist_func_t<float> Kernel<Metric::L2, DataType::SQ8_FP32, Tier::AVX2>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_L2SqrSIMD16_AVX2);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::IP, DataType::SQ8_FP32, Tier::AVX2>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_InnerProductSIMD16_AVX2);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::AVX2>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_CosineSIMD16_AVX2);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/AVX2.h b/src/VecSim/spaces/functions/AVX2.h
index 081c42a4e..c6b761d0b 100644
--- a/src/VecSim/spaces/functions/AVX2.h
+++ b/src/VecSim/spaces/functions/AVX2.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -19,4 +20,15 @@ dist_func_t<float> Choose_SQ8_FP32_L2_implementation_AVX2(size_t dim);
 dist_func_t<float> Choose_BF16_IP_implementation_AVX2(size_t dim);
 dist_func_t<float> Choose_BF16_L2_implementation_AVX2(size_t dim);
 
+// What this tier provides, one row per (metric, type). The values come from what the kernels
+// actually do: CHOOSE_IMPLEMENTATION specializes on dim % 32 here, and the alignment hint is only
+// requested when dim % 8 == 0 because the SQ8 operand is read in 8-byte chunks. min_dim is 8
+// because below that the residual handling has nothing to work with and the scalar kernel is at
+// least as fast.
+//
+//            metric  type      tier  step  policy        align_mod  align_bytes  min_dim
+VECSIM_KERNEL(L2, SQ8_FP32, AVX2, 32, FixedModulus, 8, 8, 8)
+VECSIM_KERNEL(IP, SQ8_FP32, AVX2, 32, FixedModulus, 8, 8, 8)
+VECSIM_KERNEL(Cosine, SQ8_FP32, AVX2, 32, FixedModulus, 8, 8, 8)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/AVX2_FMA.cpp b/src/VecSim/spaces/functions/AVX2_FMA.cpp
index 0eaacd070..25dcf859e 100644
--- a/src/VecSim/spaces/functions/AVX2_FMA.cpp
+++ b/src/VecSim/spaces/functions/AVX2_FMA.cpp
@@ -31,6 +31,27 @@ dist_func_t<float> Choose_SQ8_FP32_L2_implementation_AVX2_FMA(size_t dim) {
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. Inside the region where the chooser macro is defined,
+// and in the only translation unit compiled with this tier's flags. Each body is the
+// legacy chooser's macro invocation unchanged, so the selected kernel cannot differ.
+dist_func_t<float> Kernel<Metric::L2, DataType::SQ8_FP32, Tier::AVX2_FMA>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_L2SqrSIMD16_AVX2_FMA);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::IP, DataType::SQ8_FP32, Tier::AVX2_FMA>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_InnerProductSIMD16_AVX2_FMA);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::AVX2_FMA>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_CosineSIMD16_AVX2_FMA);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/AVX2_FMA.h b/src/VecSim/spaces/functions/AVX2_FMA.h
index b20b1a588..0c77b305c 100644
--- a/src/VecSim/spaces/functions/AVX2_FMA.h
+++ b/src/VecSim/spaces/functions/AVX2_FMA.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -16,4 +17,10 @@ dist_func_t<float> Choose_SQ8_FP32_IP_implementation_AVX2_FMA(size_t dim);
 dist_func_t<float> Choose_SQ8_FP32_Cosine_implementation_AVX2_FMA(size_t dim);
 dist_func_t<float> Choose_SQ8_FP32_L2_implementation_AVX2_FMA(size_t dim);
 
+// What this tier provides, one row per (metric, type). Values taken from the legacy
+//            metric  type      tier  step  policy  align_mod  align_bytes  min_dim
+VECSIM_KERNEL(L2, SQ8_FP32, AVX2_FMA, 32, FixedModulus, 8, 8, 8)
+VECSIM_KERNEL(IP, SQ8_FP32, AVX2_FMA, 32, FixedModulus, 8, 8, 8)
+VECSIM_KERNEL(Cosine, SQ8_FP32, AVX2_FMA, 32, FixedModulus, 8, 8, 8)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.cpp b/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.cpp
index 97da55546..0be59fa1a 100644
--- a/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.cpp
+++ b/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.cpp
@@ -94,6 +94,30 @@ dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_AVX512F_BW_VL_VNNI(size_t di
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. Inside the region where the chooser macro is defined,
+// and in the only translation unit compiled with this tier's flags. Each body is the
+// legacy chooser's macro invocation unchanged, so the selected kernel cannot differ.
+dist_func_t<float>
+Kernel<Metric::L2, DataType::SQ8_FP32, Tier::AVX512_F_BW_VL_VNNI>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_L2SqrSIMD16_AVX512F_BW_VL_VNNI);
+    return ret_dist_func;
+}
+
+dist_func_t<float>
+Kernel<Metric::IP, DataType::SQ8_FP32, Tier::AVX512_F_BW_VL_VNNI>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_InnerProductSIMD16_AVX512F_BW_VL_VNNI);
+    return ret_dist_func;
+}
+
+dist_func_t<float>
+Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::AVX512_F_BW_VL_VNNI>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 32, SQ8_FP32_CosineSIMD16_AVX512F_BW_VL_VNNI);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.h b/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.h
index fe1583491..032cbc890 100644
--- a/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.h
+++ b/src/VecSim/spaces/functions/AVX512F_BW_VL_VNNI.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -29,4 +30,11 @@ dist_func_t<float> Choose_SQ8_SQ8_IP_implementation_AVX512F_BW_VL_VNNI(size_t di
 dist_func_t<float> Choose_SQ8_SQ8_Cosine_implementation_AVX512F_BW_VL_VNNI(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_AVX512F_BW_VL_VNNI(size_t dim);
 
+// What this tier provides, one row per (metric, type). Values taken from the legacy chooser.
+// The tier name and the file stem differ here (AVX512_F_BW_VL_VNNI against
+// AVX512F_BW_VL_VNNI), which is why the manifest carries the stem as its own column.
+VECSIM_KERNEL(L2, SQ8_FP32, AVX512_F_BW_VL_VNNI, 32, FixedModulus, 16, 16, 8)
+VECSIM_KERNEL(IP, SQ8_FP32, AVX512_F_BW_VL_VNNI, 32, FixedModulus, 16, 16, 8)
+VECSIM_KERNEL(Cosine, SQ8_FP32, AVX512_F_BW_VL_VNNI, 32, FixedModulus, 16, 16, 8)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/NEON.cpp b/src/VecSim/spaces/functions/NEON.cpp
index 0c9a286e3..0d53da160 100644
--- a/src/VecSim/spaces/functions/NEON.cpp
+++ b/src/VecSim/spaces/functions/NEON.cpp
@@ -7,6 +7,21 @@
  * GNU Affero General Public License v3 (AGPLv3).
  */
 #include "NEON.h"
+
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_neon.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/L2/L2_NEON_FP32.h"
 #include "VecSim/spaces/IP/IP_NEON_FP32.h"
 #include "VecSim/spaces/L2/L2_NEON_INT8.h"
@@ -19,6 +34,7 @@
 #include "VecSim/spaces/IP/IP_NEON_SQ8_FP32.h"
 #include "VecSim/spaces/IP/IP_NEON_SQ8_SQ8.h"
 #include "VecSim/spaces/L2/L2_NEON_SQ8_SQ8.h"
+} // namespace
 
 namespace spaces {
 
@@ -121,6 +137,27 @@ dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_NEON(size_t dim) {
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. Inside the region where the chooser macro is defined,
+// and in the only translation unit compiled with this tier's flags. Each body is the
+// legacy chooser's macro invocation unchanged, so the selected kernel cannot differ.
+dist_func_t<float> Kernel<Metric::L2, DataType::SQ8_FP32, Tier::NEON>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 16, SQ8_FP32_L2SqrSIMD16_NEON);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::IP, DataType::SQ8_FP32, Tier::NEON>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 16, SQ8_FP32_InnerProductSIMD16_NEON);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::NEON>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 16, SQ8_FP32_CosineSIMD16_NEON);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/NEON.h b/src/VecSim/spaces/functions/NEON.h
index 08060b402..494147a6e 100644
--- a/src/VecSim/spaces/functions/NEON.h
+++ b/src/VecSim/spaces/functions/NEON.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -35,4 +36,10 @@ dist_func_t<float> Choose_SQ8_SQ8_IP_implementation_NEON(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_Cosine_implementation_NEON(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_NEON(size_t dim);
 
+// What this tier provides, one row per (metric, type). Values taken from the legacy
+//            metric  type      tier  step  policy  align_mod  align_bytes  min_dim
+VECSIM_KERNEL(L2, SQ8_FP32, NEON, 16, FixedModulus, 0, 0, 1)
+VECSIM_KERNEL(IP, SQ8_FP32, NEON, 16, FixedModulus, 0, 0, 1)
+VECSIM_KERNEL(Cosine, SQ8_FP32, NEON, 16, FixedModulus, 0, 0, 1)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/NEON_BF16.cpp b/src/VecSim/spaces/functions/NEON_BF16.cpp
index 4de205bb8..1a515943e 100644
--- a/src/VecSim/spaces/functions/NEON_BF16.cpp
+++ b/src/VecSim/spaces/functions/NEON_BF16.cpp
@@ -8,8 +8,23 @@
  */
 #include "NEON_BF16.h"
 
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_neon.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/L2/L2_NEON_BF16.h"
 #include "VecSim/spaces/IP/IP_NEON_BF16.h"
+} // namespace
 
 namespace spaces {
 
diff --git a/src/VecSim/spaces/functions/NEON_DOTPROD.cpp b/src/VecSim/spaces/functions/NEON_DOTPROD.cpp
index 12f762093..ade17bb31 100644
--- a/src/VecSim/spaces/functions/NEON_DOTPROD.cpp
+++ b/src/VecSim/spaces/functions/NEON_DOTPROD.cpp
@@ -7,12 +7,28 @@
  * GNU Affero General Public License v3 (AGPLv3).
  */
 #include "NEON.h"
+
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_neon.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/IP/IP_NEON_DOTPROD_INT8.h"
 #include "VecSim/spaces/IP/IP_NEON_DOTPROD_UINT8.h"
 #include "VecSim/spaces/IP/IP_NEON_DOTPROD_SQ8_SQ8.h"
 #include "VecSim/spaces/L2/L2_NEON_DOTPROD_INT8.h"
 #include "VecSim/spaces/L2/L2_NEON_DOTPROD_UINT8.h"
 #include "VecSim/spaces/L2/L2_NEON_DOTPROD_SQ8_SQ8.h"
+} // namespace
 
 namespace spaces {
 
diff --git a/src/VecSim/spaces/functions/NEON_FHM.cpp b/src/VecSim/spaces/functions/NEON_FHM.cpp
index 2beceed0c..ed92bec47 100644
--- a/src/VecSim/spaces/functions/NEON_FHM.cpp
+++ b/src/VecSim/spaces/functions/NEON_FHM.cpp
@@ -8,8 +8,23 @@
  */
 #include "NEON_FHM.h"
 
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_neon.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/IP/IP_NEON_SQ8_FP16.h"
 #include "VecSim/spaces/L2/L2_NEON_SQ8_FP16.h"
+} // namespace
 
 namespace spaces {
 
diff --git a/src/VecSim/spaces/functions/NEON_HP.cpp b/src/VecSim/spaces/functions/NEON_HP.cpp
index 20d93a517..412963066 100644
--- a/src/VecSim/spaces/functions/NEON_HP.cpp
+++ b/src/VecSim/spaces/functions/NEON_HP.cpp
@@ -8,10 +8,25 @@
  */
 #include "NEON_HP.h"
 
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_neon.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/L2/L2_NEON_FP16.h"
 #include "VecSim/spaces/IP/IP_NEON_FP16.h"
 #include "VecSim/spaces/IP/IP_NEON_SQ8_FP16.h"
 #include "VecSim/spaces/L2/L2_NEON_SQ8_FP16.h"
+} // namespace
 
 namespace spaces {
 
diff --git a/src/VecSim/spaces/functions/SSE4.cpp b/src/VecSim/spaces/functions/SSE4.cpp
index 5f5bbc1ba..699fa82e3 100644
--- a/src/VecSim/spaces/functions/SSE4.cpp
+++ b/src/VecSim/spaces/functions/SSE4.cpp
@@ -32,6 +32,27 @@ dist_func_t<float> Choose_SQ8_FP32_L2_implementation_SSE4(size_t dim) {
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. Inside the region where the chooser macro is defined,
+// and in the only translation unit compiled with this tier's flags. Each body is the
+// legacy chooser's macro invocation unchanged, so the selected kernel cannot differ.
+dist_func_t<float> Kernel<Metric::L2, DataType::SQ8_FP32, Tier::SSE4>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 16, SQ8_FP32_L2SqrSIMD16_SSE4);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::IP, DataType::SQ8_FP32, Tier::SSE4>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 16, SQ8_FP32_InnerProductSIMD16_SSE4);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::SSE4>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_IMPLEMENTATION(ret_dist_func, dim, 16, SQ8_FP32_CosineSIMD16_SSE4);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/SSE4.h b/src/VecSim/spaces/functions/SSE4.h
index e47948137..edbc41187 100644
--- a/src/VecSim/spaces/functions/SSE4.h
+++ b/src/VecSim/spaces/functions/SSE4.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -16,4 +17,10 @@ dist_func_t<float> Choose_SQ8_FP32_IP_implementation_SSE4(size_t dim);
 dist_func_t<float> Choose_SQ8_FP32_Cosine_implementation_SSE4(size_t dim);
 dist_func_t<float> Choose_SQ8_FP32_L2_implementation_SSE4(size_t dim);
 
+// What this tier provides, one row per (metric, type). Values taken from the legacy
+//            metric  type      tier  step  policy  align_mod  align_bytes  min_dim
+VECSIM_KERNEL(L2, SQ8_FP32, SSE4, 16, FixedModulus, 4, 4, 8)
+VECSIM_KERNEL(IP, SQ8_FP32, SSE4, 16, FixedModulus, 4, 4, 8)
+VECSIM_KERNEL(Cosine, SQ8_FP32, SSE4, 16, FixedModulus, 4, 4, 8)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/SVE.cpp b/src/VecSim/spaces/functions/SVE.cpp
index bd197c84c..8ca6f423c 100644
--- a/src/VecSim/spaces/functions/SVE.cpp
+++ b/src/VecSim/spaces/functions/SVE.cpp
@@ -8,6 +8,21 @@
  */
 #include "SVE.h"
 
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_sve.h>
+#include <arm_neon.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/L2/L2_SVE_FP32.h"
 #include "VecSim/spaces/IP/IP_SVE_FP32.h"
 
@@ -30,6 +45,7 @@
 
 #include "VecSim/spaces/IP/IP_SVE_SQ8_SQ8.h"
 #include "VecSim/spaces/L2/L2_SVE_SQ8_SQ8.h"
+} // namespace
 
 namespace spaces {
 
@@ -160,6 +176,27 @@ dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_SVE(size_t dim) {
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. Inside the region where the chooser macro is defined,
+// and in the only translation unit compiled with this tier's flags. Each body is the
+// legacy chooser's macro invocation unchanged, so the selected kernel cannot differ.
+dist_func_t<float> Kernel<Metric::L2, DataType::SQ8_FP32, Tier::SVE>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_SVE_IMPLEMENTATION(ret_dist_func, SQ8_FP32_L2SqrSIMD_SVE, dim, svcntw);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::IP, DataType::SQ8_FP32, Tier::SVE>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_SVE_IMPLEMENTATION(ret_dist_func, SQ8_FP32_InnerProductSIMD_SVE, dim, svcntw);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::SVE>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_SVE_IMPLEMENTATION(ret_dist_func, SQ8_FP32_CosineSIMD_SVE, dim, svcntw);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/SVE.h b/src/VecSim/spaces/functions/SVE.h
index 43b3b22cd..e0c3bb80d 100644
--- a/src/VecSim/spaces/functions/SVE.h
+++ b/src/VecSim/spaces/functions/SVE.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -42,4 +43,10 @@ dist_func_t<float> Choose_SQ8_SQ8_IP_implementation_SVE(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_Cosine_implementation_SVE(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_SVE(size_t dim);
 
+// What this tier provides, one row per (metric, type). Values taken from the legacy
+//            metric  type      tier  step  policy  align_mod  align_bytes  min_dim
+VECSIM_KERNEL(L2, SQ8_FP32, SVE, 0, SveRuntime, 0, 0, 1)
+VECSIM_KERNEL(IP, SQ8_FP32, SVE, 0, SveRuntime, 0, 0, 1)
+VECSIM_KERNEL(Cosine, SQ8_FP32, SVE, 0, SveRuntime, 0, 0, 1)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/SVE2.cpp b/src/VecSim/spaces/functions/SVE2.cpp
index 9eea81523..17bd81cb0 100644
--- a/src/VecSim/spaces/functions/SVE2.cpp
+++ b/src/VecSim/spaces/functions/SVE2.cpp
@@ -8,6 +8,20 @@
  */
 #include "SVE2.h"
 
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_sve.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/L2/L2_SVE_FP32.h"
 #include "VecSim/spaces/IP/IP_SVE_FP32.h"
 
@@ -26,6 +40,7 @@
 #include "VecSim/spaces/L2/L2_SVE2_SQ8_FP16.h" // SVE2 fast path: FMLALB/FMLALT widening
 #include "VecSim/spaces/IP/IP_SVE_SQ8_SQ8.h"   // SVE2 implementation is identical to SVE
 #include "VecSim/spaces/L2/L2_SVE_SQ8_SQ8.h"   // SVE2 implementation is identical to SVE
+} // namespace
 
 namespace spaces {
 
@@ -156,6 +171,27 @@ dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_SVE2(size_t dim) {
     return ret_dist_func;
 }
 
+// Kernel<>::make() for this tier. Inside the region where the chooser macro is defined,
+// and in the only translation unit compiled with this tier's flags. Each body is the
+// legacy chooser's macro invocation unchanged, so the selected kernel cannot differ.
+dist_func_t<float> Kernel<Metric::L2, DataType::SQ8_FP32, Tier::SVE2>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_SVE_IMPLEMENTATION(ret_dist_func, SQ8_FP32_L2SqrSIMD_SVE, dim, svcntw);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::IP, DataType::SQ8_FP32, Tier::SVE2>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_SVE_IMPLEMENTATION(ret_dist_func, SQ8_FP32_InnerProductSIMD_SVE, dim, svcntw);
+    return ret_dist_func;
+}
+
+dist_func_t<float> Kernel<Metric::Cosine, DataType::SQ8_FP32, Tier::SVE2>::make(size_t dim) {
+    dist_func_t<float> ret_dist_func;
+    CHOOSE_SVE_IMPLEMENTATION(ret_dist_func, SQ8_FP32_CosineSIMD_SVE, dim, svcntw);
+    return ret_dist_func;
+}
+
 #include "implementation_chooser_cleanup.h"
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/SVE2.h b/src/VecSim/spaces/functions/SVE2.h
index 2c1bfbac3..0925b09f0 100644
--- a/src/VecSim/spaces/functions/SVE2.h
+++ b/src/VecSim/spaces/functions/SVE2.h
@@ -9,6 +9,7 @@
 #pragma once
 
 #include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/kernel.h"
 
 namespace spaces {
 
@@ -42,4 +43,10 @@ dist_func_t<float> Choose_SQ8_SQ8_IP_implementation_SVE2(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_Cosine_implementation_SVE2(size_t dim);
 dist_func_t<float> Choose_SQ8_SQ8_L2_implementation_SVE2(size_t dim);
 
+// What this tier provides, one row per (metric, type). Values taken from the legacy
+//            metric  type      tier  step  policy  align_mod  align_bytes  min_dim
+VECSIM_KERNEL(L2, SQ8_FP32, SVE2, 0, SveRuntime, 0, 0, 1)
+VECSIM_KERNEL(IP, SQ8_FP32, SVE2, 0, SveRuntime, 0, 0, 1)
+VECSIM_KERNEL(Cosine, SQ8_FP32, SVE2, 0, SveRuntime, 0, 0, 1)
+
 } // namespace spaces
diff --git a/src/VecSim/spaces/functions/SVE_BF16.cpp b/src/VecSim/spaces/functions/SVE_BF16.cpp
index b457cdb7f..d7b9a6994 100644
--- a/src/VecSim/spaces/functions/SVE_BF16.cpp
+++ b/src/VecSim/spaces/functions/SVE_BF16.cpp
@@ -8,8 +8,23 @@
  */
 #include "SVE_BF16.h"
 
+// Hoisted above the anonymous namespace below so that the standard library and the shared
+// type headers keep external linkage. Wrapping them would pull <cstring> and friends into
+// the anonymous namespace and fail to compile.
+#include "VecSim/spaces/space_includes.h"
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/types/bfloat16.h"
+#include "VecSim/types/float16.h"
+#include "VecSim/types/sq8.h"
+#include <arm_sve.h>
+
+// Kernel instantiations get internal linkage, unique to this translation unit, so two tiers
+// that share a kernel header cannot emit the same weak symbol and let link order pick the
+// body. Only this tier's Choose_* entry points stay external.
+namespace {
 #include "VecSim/spaces/IP/IP_SVE_BF16.h"
 #include "VecSim/spaces/L2/L2_SVE_BF16.h"
+} // namespace
 
 namespace spaces {
 
diff --git a/src/VecSim/spaces/isa_features.def b/src/VecSim/spaces/isa_features.def
new file mode 100644
index 000000000..e1249731a
--- /dev/null
+++ b/src/VecSim/spaces/isa_features.def
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2006-Present, Redis Ltd.
+ * All rights reserved.
+ *
+ * Licensed under your choice of the Redis Source Available License 2.0
+ * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
+ * GNU Affero General Public License v3 (AGPLv3).
+ */
+
+// Feature-token table: one row per CPU feature, one physical line per row. A feature token is the
+// only thing a tier in isa_tiers.def is allowed to name.
+//
+// Each row carries everything needed to derive a tier's compiler flags from its token list alone,
+// and to state that tier's runtime predicate in the same vocabulary. Those stay separate axes on
+// purpose: this library is built on one machine and run on another, so what the compiler was
+// allowed to emit and what the running CPU implements are different questions. A flag fragment
+// expands to a compiler-defined bundle that differs between gcc and clang for the same -march
+// string, so a runtime predicate is never derived from flags.
+//
+// Columns:
+//   token          the name tiers use, unique across both architectures
+//   arch           X86 or ARM; a tier may only name tokens of its own architecture
+//   flag fragment  what this token contributes to the compile command. x86 unions the -m options;
+//                  ARM appends "+feature" suffixes to one -march level, since ARM -march strings
+//                  are monolithic
+//   min level      lowest -march level admitting this fragment, or "-" on x86 where there is none.
+//                  A tier's -march is the highest level in its token closure
+//   feature field  the cpu_features struct field naming the runtime bit. This column, and only
+//                  this column, feeds the runtime predicate
+//
+// There is deliberately no per-feature CXX_* probe column. The authoritative build gate is a
+// whole-tier try_compile of the tier's real source under its complete derived flags, which subsumes
+// per-flag probing and also catches a flag that passes alone but fails in the real combination.
+
+//       token          arch  flag fragment      min level    feature field
+FEATURE( SSE,           X86,  "-msse",           -,           sse          )
+FEATURE( SSE3,          X86,  "-msse3",          -,           sse3         )
+FEATURE( SSE4_1,        X86,  "-msse4.1",        -,           sse4_1       )
+FEATURE( AVX,           X86,  "-mavx",           -,           avx          )
+FEATURE( AVX2,          X86,  "-mavx2",          -,           avx2         )
+FEATURE( FMA3,          X86,  "-mfma",           -,           fma3         )
+FEATURE( F16C,          X86,  "-mf16c",          -,           f16c         )
+FEATURE( AVX512F,       X86,  "-mavx512f",       -,           avx512f      )
+FEATURE( AVX512BW,      X86,  "-mavx512bw",      -,           avx512bw     )
+FEATURE( AVX512VL,      X86,  "-mavx512vl",      -,           avx512vl     )
+FEATURE( AVX512VNNI,    X86,  "-mavx512vnni",    -,           avx512vnni   )
+FEATURE( AVX512VBMI2,   X86,  "-mavx512vbmi2",   -,           avx512vbmi2  )
+FEATURE( AVX512BF16,    X86,  "-mavx512bf16",    -,           avx512_bf16  )
+FEATURE( AVX512FP16,    X86,  "-mavx512fp16",    -,           avx512_fp16  )
+
+FEATURE( ASIMD,         ARM,  "",                armv8-a,     asimd        )
+FEATURE( FPHP,          ARM,  "+fp16",           armv8.2-a,   fphp         )
+FEATURE( ASIMDHP,       ARM,  "+fp16",           armv8.2-a,   asimdhp      )
+FEATURE( ASIMDFHM,      ARM,  "+fp16fml",        armv8.2-a,   asimdfhm     )
+FEATURE( ASIMDDP,       ARM,  "+dotprod",        armv8.2-a,   asimddp      )
+FEATURE( BF16,          ARM,  "+bf16",           armv8.2-a,   bf16         )
+FEATURE( SVE,           ARM,  "+sve",            armv8-a,     sve          )
+FEATURE( SVE2,          ARM,  "+sve2",           armv9-a,     sve2         )
+FEATURE( SVEBF16,       ARM,  "+bf16",           armv8.2-a,   svebf16      )
+
+// Three distinct relations, spelled distinctly. A bare "implies" would conflate them, and they
+// answer different questions: which CPU masks are possible, what a flag fragment forces the
+// compiler to assume, and what raising the -march level forces.
+
+// ARCH_IMPLIES: if the left bit is set on a CPU then the right one is too. Used ONLY to enumerate
+// the CPU masks worth testing, never to shorten a runtime predicate.
+ARCH_IMPLIES(   AVX2,        AVX             )
+ARCH_IMPLIES(   AVX512BW,    AVX512F         )
+ARCH_IMPLIES(   AVX512VL,    AVX512F         )
+ARCH_IMPLIES(   AVX512VNNI,  AVX512F         )
+ARCH_IMPLIES(   AVX512VBMI2, AVX512BW        )
+ARCH_IMPLIES(   AVX512BF16,  AVX512F         )
+ARCH_IMPLIES(   AVX512FP16,  AVX512F         )
+ARCH_IMPLIES(   SSE4_1,      SSE3            )
+ARCH_IMPLIES(   SSE3,        SSE             )
+ARCH_IMPLIES(   ASIMDFHM,    ASIMDHP         )
+ARCH_IMPLIES(   ASIMDHP,     FPHP            )
+ARCH_IMPLIES(   SVE2,        SVE             )
+ARCH_IMPLIES(   SVEBF16,     SVE             )
+
+// FLAG_ENABLES: passing the left fragment makes the compiler assume the right capabilities,
+// whatever the tier asked for. This is why a predicate cannot be derived from flags. F16C is
+// VEX-encoded, so -mf16c forces AVX state, and "+fp16" is one fragment covering two HWCAPs.
+FLAG_ENABLES(   F16C,        AVX             )
+FLAG_ENABLES(   "+fp16",     ASIMDHP+FPHP    )
+FLAG_ENABLES(   "+bf16",     BF16+SVEBF16    )
+
+// LEVEL_REQUIRES: what raising the -march level itself forces, independent of any +fragment.
+LEVEL_REQUIRES( armv8.1-a,   ATOMICS+CRC32+QRDMX )
+LEVEL_REQUIRES( armv8.2-a,   ATOMICS+CRC32+QRDMX )
diff --git a/src/VecSim/spaces/isa_tiers.def b/src/VecSim/spaces/isa_tiers.def
new file mode 100644
index 000000000..91d002ea6
--- /dev/null
+++ b/src/VecSim/spaces/isa_tiers.def
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-Present, Redis Ltd.
+ * All rights reserved.
+ *
+ * Licensed under your choice of the Redis Source Available License 2.0
+ * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
+ * GNU Affero General Public License v3 (AGPLv3).
+ */
+
+// Tier table: one row per SIMD tier, one physical line per row. Every token named here must exist
+// in isa_features.def and belong to the same architecture as the tier.
+//
+// Columns:
+//   tier         the tier's name in C++, as TierInfo<Tier> and VECSIM_BUILT_<TIER>
+//   arch         X86 or ARM
+//   stem         file stem under spaces/functions/, so <stem>.cpp and <stem>.h. Deliberately the
+//                file stem and not the tier name, because the two differ today (tier
+//                AVX512_F_BW_VL_VNNI lives in AVX512F_BW_VL_VNNI.cpp) and renaming files is not
+//                this refactor's job
+//   priority     higher wins when several tiers are eligible. Values are spaced by 10 so a tier can
+//                be inserted between two others without renumbering the table
+//   FLAGS_FROM   tokens whose flag fragments build the compile command
+//   GUARANTEES   tokens whose feature fields build the runtime predicate
+//
+// FLAGS_FROM and GUARANTEES are separate columns rather than one list, and this is the crux of the
+// whole design. A flag fragment expands to a compiler-defined bundle, so compiling with a flag does
+// not tell you which bits the deployment CPU must have. Two live bugs came from conflating them: a
+// tier compiled at +fp16fml but dispatched on asimdhp alone emitted FMLAL into a path reachable on
+// cores without FEAT_FHM, and six AVX512 VNNI dispatch sites omitted avx512vl while the tier was
+// compiled with -mavx512vl. Where the columns differ, the difference is load-bearing and commented.
+
+//    tier                 arch stem                prio   FLAGS_FROM                                 GUARANTEES
+TIER( AVX512BF16_VL,       X86, AVX512BF16_VL,      100,  (AVX512BF16, AVX512VL),                    (AVX512BF16, AVX512VL) )
+TIER( AVX512FP16_VL,       X86, AVX512FP16_VL,       95,  (AVX512FP16, AVX512VL),                    (AVX512FP16, AVX512VL) )
+TIER( AVX512_BW_VBMI2,     X86, AVX512BW_VBMI2,      90,  (AVX512BW, AVX512VBMI2),                   (AVX512BW, AVX512VBMI2) )
+// GUARANTEES lists AVX512VL because the tier is compiled with -mavx512vl and may therefore contain
+// VL-encoded instructions. Six of the twelve legacy dispatch sites omitted that bit.
+TIER( AVX512_F_BW_VL_VNNI, X86, AVX512F_BW_VL_VNNI,  85,  (AVX512F, AVX512BW, AVX512VL, AVX512VNNI), (AVX512F, AVX512BW, AVX512VL, AVX512VNNI) )
+TIER( AVX512F,             X86, AVX512F,             80,  (AVX512F),                                 (AVX512F) )
+// AVX2_F16C, AVX2_FMA_F16C and SSE4_F16C are separate tiers rather than variants of AVX2, AVX2_FMA
+// and SSE4, because each is its own translation unit with its own flags and its own predicate. They
+// carry the SQ8-to-FP16 kernels, which need vcvtph2ps and so need F16C, while the plain AVX2 and
+// SSE4 tiers carry the SQ8-to-FP32 kernels that do not. Legacy code expressed this as one shared
+// OPT_F16C guard wrapped around three differently-predicated branches.
+TIER( AVX2_FMA_F16C,       X86, AVX2_FMA_F16C,       70,  (AVX2, FMA3, F16C),                        (AVX2, FMA3, F16C) )
+TIER( AVX2_FMA,            X86, AVX2_FMA,            65,  (AVX2, FMA3),                              (AVX2, FMA3) )
+TIER( AVX2_F16C,           X86, AVX2_F16C,           60,  (AVX2, F16C),                              (AVX2, F16C) )
+TIER( AVX2,                X86, AVX2,                55,  (AVX2),                                    (AVX2) )
+// Compiled "-mf16c -mfma -mavx" and dispatched on f16c && fma3 && avx, so here the two columns
+// agree. Worth stating because -mf16c is VEX-encoded and forces AVX state, so a tier naming only
+// F16C would still be handed AVX by the compiler; this tier asks for all three explicitly.
+TIER( F16C,                X86, F16C,                50,  (F16C, FMA3, AVX),                         (F16C, FMA3, AVX) )
+TIER( AVX,                 X86, AVX,                 45,  (AVX),                                     (AVX) )
+// Compiled "-msse4.1 -mavx -mf16c" and dispatched on sse4_1 && f16c && avx. The AVX bit is in the
+// predicate because the flag put AVX-state instructions in reach, not because the kernels asked
+// for SSE4 plus AVX: this is FLAG_ENABLES(F16C, AVX) showing up in a real predicate.
+TIER( SSE4_F16C,           X86, SSE4_F16C,           40,  (SSE4_1, AVX, F16C),                       (SSE4_1, F16C, AVX) )
+TIER( SSE4,                X86, SSE4,                35,  (SSE4_1),                                  (SSE4_1) )
+TIER( SSE3,                X86, SSE3,                30,  (SSE3),                                    (SSE3) )
+TIER( SSE,                 X86, SSE,                 25,  (SSE),                                     (SSE) )
+
+TIER( SVE2,                ARM, SVE2,               100,  (SVE2),                                    (SVE2) )
+TIER( SVE_BF16,            ARM, SVE_BF16,            95,  (SVE, BF16),                               (SVE, SVEBF16) )
+TIER( SVE,                 ARM, SVE,                 90,  (SVE),                                     (SVE) )
+TIER( NEON_BF16,           ARM, NEON_BF16,           80,  (BF16),                                    (BF16) )
+// The tier that motivated splitting these columns. It is compiled at +fp16fml, so gcc contracts a
+// widening convert plus FMA into FMLAL anywhere in the translation unit, and FEAT_FHM is optional in
+// armv8.2-a. Dispatching it on asimdhp alone was a SIGILL on any core without FEAT_FHM.
+TIER( NEON_FHM,            ARM, NEON_FHM,            75,  (ASIMDFHM),                                (ASIMDHP, ASIMDFHM) )
+TIER( NEON_HP,             ARM, NEON_HP,             70,  (ASIMDHP),                                 (ASIMDHP) )
+TIER( NEON_DOTPROD,        ARM, NEON_DOTPROD,        65,  (ASIMDDP),                                 (ASIMDDP) )
+TIER( NEON,                ARM, NEON,                60,  (ASIMD),                                   (ASIMD) )
diff --git a/src/VecSim/spaces/kernel.h b/src/VecSim/spaces/kernel.h
new file mode 100644
index 000000000..df4704d20
--- /dev/null
+++ b/src/VecSim/spaces/kernel.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2006-Present, Redis Ltd.
+ * All rights reserved.
+ *
+ * Licensed under your choice of the Redis Source Available License 2.0
+ * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
+ * GNU Affero General Public License v3 (AGPLv3).
+ */
+#pragma once
+
+// What a tier provides for one (metric, data type) pair, and the per-type rules that hold whatever
+// tier is chosen. Like tier_info.h this header names no intrinsics: the specializations live in the
+// per-tier declaration headers and their make() bodies live in the tier's own translation unit, the
+// only one compiled with that tier's flags.
+
+#include "VecSim/spaces/spaces.h"
+#include "VecSim/spaces/tier_info.h"
+
+#include <cstddef>
+#include <limits>
+
+namespace spaces {
+
+enum class Metric { L2, IP, Cosine };
+
+// The stored/query type pair a kernel works on. SQ8_FP32 means SQ8 storage against an FP32 query,
+// and so on for the other asymmetric combinations.
+enum class DataType { FP32, FP64, BF16, FP16, INT8, UINT8, SQ8_FP32, SQ8_FP16, SQ8_SQ8 };
+
+// How a kernel's tail is handled. FixedModulus selects a compile-time specialization on
+// dim % residual_mod, which is what CHOOSE_IMPLEMENTATION does. SveRuntime defers to the runtime
+// vector length, which is what CHOOSE_SVE_IMPLEMENTATION does, so residual_mod is not meaningful.
+enum class ResidualPolicy { FixedModulus, SveRuntime };
+
+// Unspecialized primary: this tier does not provide this (metric, type). dispatch() skips it, and
+// because the check is `if constexpr (Kernel<...>::exists)`, make() is never referenced for a
+// combination that does not exist and never linked for a tier that did not compile.
+template <Metric M, DataType D, Tier T>
+struct Kernel {
+    static constexpr bool exists = false;
+};
+
+// Per-type rules that hold regardless of tier. Two kinds, both real in the current code:
+// a predicate gate (BF16 needs a little-endian host) and a dimension ceiling (the uint8 families
+// stop being exact past UINT8_MAX_EXACT_SIMD_DIM because every SIMD kernel accumulates into a
+// signed 32-bit total, while the scalar kernel accumulates into 64 bits).
+template <DataType D>
+struct TypePolicy {
+    static bool eligible() { return true; }
+    static constexpr size_t simd_max_dim = std::numeric_limits<size_t>::max();
+};
+
+// Declares what a tier provides for one (metric, type). Kept as a macro so a tier header reads as a
+// short table of rows and a contributor adding a kernel copies a neighbouring line rather than
+// writing a template specialization.
+//
+//   residual_step  the modulus CHOOSE_IMPLEMENTATION specializes on, or 0 under SveRuntime
+//   policy         FixedModulus or SveRuntime
+//   align_modulus  alignment is only worth requesting when dim % align_modulus == 0, since a
+//                  residual offsets every subsequent load anyway. 0 means this kernel never asks
+//   align_byte_cnt the hint to publish when the modulus divides, in bytes
+//   minimum_dim    below this the scalar kernel is at least as fast, so the tier declines
+#define VECSIM_KERNEL(metric, type, tier, residual_step, policy, align_modulus, align_byte_cnt,    \
+                      minimum_dim)                                                                 \
+    template <>                                                                                    \
+    struct Kernel<Metric::metric, DataType::type, Tier::tier> {                                    \
+        static constexpr bool exists = true;                                                       \
+        static constexpr size_t residual_mod = residual_step;                                      \
+        static constexpr ResidualPolicy residual_policy = ResidualPolicy::policy;                  \
+        static constexpr size_t align_mod = align_modulus;                                         \
+        static constexpr size_t align_bytes = align_byte_cnt;                                      \
+        static constexpr size_t min_dim = minimum_dim;                                             \
+        static constexpr size_t max_dim = std::numeric_limits<size_t>::max();                      \
+        static dist_func_t<float> make(size_t dim);                                                \
+    };
+
+} // namespace spaces
diff --git a/src/VecSim/spaces/spaces.h b/src/VecSim/spaces/spaces.h
index 735e40e89..3b9a7071d 100644
--- a/src/VecSim/spaces/spaces.h
+++ b/src/VecSim/spaces/spaces.h
@@ -13,7 +13,9 @@
 
 #include <cassert>
 #include <cstdint>
+#include <cstring>
 #include <limits>
+#include <type_traits>
 
 namespace spaces {
 
@@ -65,16 +67,57 @@ static constexpr size_t UINT8_MAX_EXACT_SIMD_DIM =
     std::numeric_limits<int32_t>::max() /
     (std::numeric_limits<uint8_t>::max() * std::numeric_limits<uint8_t>::max());
 
+// Intersect an overridden feature mask with the features actually detected on this machine, so
+// that the override can only clear a capability, never claim one the hardware does not have.
+//
+// `arch_opt` (below) is a test-only affordance: no production caller passes a non-null value
+// (every chooser in spaces.cpp calls getCpuOptimizationFeatures() with the `= nullptr` default),
+// tests use it to force a specific SIMD tier onto whatever machine runs the suite. Without this
+// intersection, a test that claims a feature the real CPU lacks would hand back a function
+// pointer into a tier that executes an illegal instruction.
+//
+// This is sound only because cpu_features::X86Features and cpu_features::Aarch64Features are
+// composed entirely of `int <name> : 1;` bitfields with no other members, so a byte-wise AND of
+// the two object representations performs a per-feature logical AND. The
+// CpuFeatureIntersection.* tests in test_spaces.cpp walk every feature via cpu_features' own
+// GetX86FeaturesEnumValue / GetAarch64FeaturesEnumValue readers and enforce that layout
+// assumption, so this breaks loudly if cpu_features ever adds a non-bitfield member.
+template <typename FeaturesType>
+static inline FeaturesType intersectWithDetectedFeatures(const FeaturesType &overridden,
+                                                         const FeaturesType &detected) {
+    static_assert(std::is_trivially_copyable_v<FeaturesType>,
+                  "byte-wise AND requires a trivially copyable features type");
+    unsigned char overridden_bytes[sizeof(FeaturesType)];
+    unsigned char detected_bytes[sizeof(FeaturesType)];
+    std::memcpy(overridden_bytes, &overridden, sizeof(FeaturesType));
+    std::memcpy(detected_bytes, &detected, sizeof(FeaturesType));
+    for (size_t i = 0; i < sizeof(FeaturesType); i++) {
+        overridden_bytes[i] &= detected_bytes[i];
+    }
+    FeaturesType result;
+    std::memcpy(&result, overridden_bytes, sizeof(FeaturesType));
+    return result;
+}
+
+// The CPU feature set for the architecture being built, at namespace scope so callers other than
+// getCpuOptimizationFeatures() can name the type without repeating the architecture selection.
+#if defined(CPU_FEATURES_ARCH_AARCH64)
+using FeaturesType = cpu_features::Aarch64Features;
+#else
+using FeaturesType = cpu_features::X86Features; // Fallback
+#endif
+
 static inline auto getCpuOptimizationFeatures(const void *arch_opt = nullptr) {
 
 #if defined(CPU_FEATURES_ARCH_AARCH64)
-    using FeaturesType = cpu_features::Aarch64Features;
     constexpr auto getFeatures = cpu_features::GetAarch64Info;
 #else
-    using FeaturesType = cpu_features::X86Features; // Fallback
     constexpr auto getFeatures = cpu_features::GetX86Info;
 #endif
-    return arch_opt ? *static_cast<const FeaturesType *>(arch_opt) : getFeatures().features;
+    const FeaturesType detected = getFeatures().features;
+    return arch_opt ? intersectWithDetectedFeatures(*static_cast<const FeaturesType *>(arch_opt),
+                                                    detected)
+                    : detected;
 }
 
 } // namespace spaces
diff --git a/src/VecSim/spaces/tier_info.h b/src/VecSim/spaces/tier_info.h
new file mode 100644
index 000000000..5a4d4dcf0
--- /dev/null
+++ b/src/VecSim/spaces/tier_info.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2006-Present, Redis Ltd.
+ * All rights reserved.
+ *
+ * Licensed under your choice of the Redis Source Available License 2.0
+ * (RSALv2); or (b) the Server Side Public License v1 (SSPLv1); or (c) the
+ * GNU Affero General Public License v3 (AGPLv3).
+ */
+#pragma once
+
+// The C++ view of isa_tiers.def and isa_features.def. Deliberately free of intrinsics: this header
+// is compiled into every translation unit that dispatches, including the baseline ones, so it may
+// only name cpu_features fields and the availability macros CMake defines.
+//
+// Two facts per tier come from two different columns and must not be conflated:
+//   compiled     from VECSIM_BUILT_<TIER>, which CMake sets from the whole-tier compile probe. It
+//                answers "did this build produce this tier's object".
+//   supported()  folded exclusively from the tier's GUARANTEES column. It answers "may the CPU in
+//                front of us execute that object".
+// supported() never consults FLAGS_FROM. A flag fragment expands to a compiler-defined bundle that
+// differs between compilers for the same -march string, so a predicate derived from flags would be
+// unsound in the one direction that matters: it would claim support the hardware does not have.
+
+#include "VecSim/spaces/spaces.h"
+
+namespace spaces {
+
+enum class Arch { X86, ARM };
+
+#if defined(CPU_FEATURES_ARCH_AARCH64)
+inline constexpr Arch kBuildArch = Arch::ARM;
+#else
+inline constexpr Arch kBuildArch = Arch::X86;
+#endif
+
+// ---- the tier enumeration, one enumerator per manifest row -----------------------------------
+#define ARCH_IMPLIES(a, b)
+#define FLAG_ENABLES(a, b)
+#define LEVEL_REQUIRES(a, b)
+#define FEATURE(token, arch, fragment, level, field)
+#define TIER(name, arch, stem, priority, flags_from, guarantees) name,
+enum class Tier {
+#include "VecSim/spaces/isa_tiers.def"
+};
+#undef TIER
+#undef FEATURE
+
+// ---- one accessor per feature token, for the current architecture only -----------------------
+// A tier may only name tokens of its own architecture (CMake enforces that), so emitting accessors
+// for the other architecture would only produce references to fields that do not exist on this
+// build's features struct.
+namespace detail {
+
+#if defined(CPU_FEATURES_ARCH_AARCH64)
+#define VECSIM_FEATURE_ARM(token, field)                                                           \
+    inline bool feature_##token(const FeaturesType &f) { return f.field; }
+#define VECSIM_FEATURE_X86(token, field)
+#else
+#define VECSIM_FEATURE_X86(token, field)                                                           \
+    inline bool feature_##token(const FeaturesType &f) { return f.field; }
+#define VECSIM_FEATURE_ARM(token, field)
+#endif
+
+#define FEATURE(token, arch, fragment, level, field) VECSIM_FEATURE_##arch(token, field)
+#include "VecSim/spaces/isa_features.def"
+#undef FEATURE
+#undef VECSIM_FEATURE_X86
+#undef VECSIM_FEATURE_ARM
+
+} // namespace detail
+
+#undef ARCH_IMPLIES
+#undef FLAG_ENABLES
+#undef LEVEL_REQUIRES
+
+// ---- folding a GUARANTEES tuple into a conjunction -------------------------------------------
+// The manifest writes GUARANTEES as a parenthesised, comma-separated tuple, so the fold is by
+// arity. Six is deliberately more than the widest row in use (four, for AVX512F+BW+VL+VNNI); a
+// seventh token fails to compile here rather than silently dropping the extra guarantees.
+#define VECSIM_AND_1(a)                ::spaces::detail::feature_##a(f)
+#define VECSIM_AND_2(a, b)             VECSIM_AND_1(a) && VECSIM_AND_1(b)
+#define VECSIM_AND_3(a, b, c)          VECSIM_AND_2(a, b) && VECSIM_AND_1(c)
+#define VECSIM_AND_4(a, b, c, d)       VECSIM_AND_3(a, b, c) && VECSIM_AND_1(d)
+#define VECSIM_AND_5(a, b, c, d, e)    VECSIM_AND_4(a, b, c, d) && VECSIM_AND_1(e)
+#define VECSIM_AND_6(a, b, c, d, e, g) VECSIM_AND_5(a, b, c, d, e) && VECSIM_AND_1(g)
+
+#define VECSIM_AND_PICK(_1, _2, _3, _4, _5, _6, NAME, ...) NAME
+#define VECSIM_ALL_OF(...)                                                                         \
+    VECSIM_AND_PICK(__VA_ARGS__, VECSIM_AND_6, VECSIM_AND_5, VECSIM_AND_4, VECSIM_AND_3,           \
+                    VECSIM_AND_2, VECSIM_AND_1)                                                    \
+    (__VA_ARGS__)
+
+// ---- TierInfo -------------------------------------------------------------------------------
+// Every tier gets a specialization, including tiers of the other architecture, so metadata stays
+// visible for tests and tooling on any build. Only the predicate body is architecture-selected.
+//
+// The selection is done by the preprocessor rather than by if constexpr, because the discarded
+// branch of an if constexpr in a non-template function still has to name things that exist, and
+// this build only emits feature accessors for its own architecture. An ARM tier's GUARANTEES
+// mention feature_SVE2 and friends, which simply are not declared in an x86 build.
+template <Tier T>
+struct TierInfo;
+
+#define VECSIM_TIER_ARCH_X86 ::spaces::Arch::X86
+#define VECSIM_TIER_ARCH_ARM ::spaces::Arch::ARM
+
+#if defined(CPU_FEATURES_ARCH_AARCH64)
+#define VECSIM_SUPPORTED_ARM(guarantees) return VECSIM_ALL_OF guarantees;
+#define VECSIM_SUPPORTED_X86(guarantees) return false;
+#else
+#define VECSIM_SUPPORTED_X86(guarantees) return VECSIM_ALL_OF guarantees;
+#define VECSIM_SUPPORTED_ARM(guarantees) return false;
+#endif
+
+#define TIER(name, arch, stem, priority, flags_from, guarantees)                                   \
+    template <>                                                                                    \
+    struct TierInfo<Tier::name> {                                                                  \
+        static constexpr Arch arch_of = VECSIM_TIER_ARCH_##arch;                                   \
+        static constexpr int priority_of = priority;                                               \
+        static constexpr bool compiled = VECSIM_BUILT_##name;                                      \
+        static constexpr const char *name_of = #name;                                              \
+        static bool supported([[maybe_unused]] const FeaturesType &f) {                            \
+            VECSIM_SUPPORTED_##arch(guarantees)                                                    \
+        }                                                                                          \
+    };
+#include "VecSim/spaces/isa_tiers.def"
+#undef TIER
+#undef VECSIM_SUPPORTED_X86
+#undef VECSIM_SUPPORTED_ARM
+#undef VECSIM_TIER_ARCH_X86
+#undef VECSIM_TIER_ARCH_ARM
+
+} // namespace spaces
diff --git a/tests/benchmark/CMakeLists.txt b/tests/benchmark/CMakeLists.txt
index 2cf536d91..db74b3023 100644
--- a/tests/benchmark/CMakeLists.txt
+++ b/tests/benchmark/CMakeLists.txt
@@ -27,7 +27,7 @@ endforeach()
 
 include(GoogleTest)
 
-if (CMAKE_HOST_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv.*)")
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv.*)")
 	include(${root}/cmake/aarch64InstructionFlags.cmake)
 	add_compile_definitions(BENCHMARK_ARCH=arm64)
 else()
diff --git a/tests/unit/CMakeLists.txt b/tests/unit/CMakeLists.txt
index c3e1cc987..16931ccbb 100644
--- a/tests/unit/CMakeLists.txt
+++ b/tests/unit/CMakeLists.txt
@@ -28,7 +28,7 @@ if(FP64_TESTS)
 	add_definitions(-DFP64_TESTS)
 endif()
 
-if (CMAKE_HOST_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv8)|(armv9)")
+if (CMAKE_SYSTEM_PROCESSOR MATCHES "(aarch64)|(arm64)|(ARM64)|(armv8)|(armv9)")
 	include(${root}/cmake/aarch64InstructionFlags.cmake)
 else()
 	include(${root}/cmake/x86_64InstructionFlags.cmake)
@@ -53,7 +53,10 @@ target_link_libraries(test_hnsw PUBLIC gtest VectorSimilarity)
 target_link_libraries(test_hnsw_parallel PUBLIC gtest VectorSimilarity)
 target_link_libraries(test_bruteforce PUBLIC gtest VectorSimilarity)
 target_link_libraries(test_allocator PUBLIC gtest VectorSimilarity)
-target_link_libraries(test_spaces PUBLIC gtest VectorSimilarity)
+# test_spaces includes spaces/tier_info.h, which needs the manifest's VECSIM_BUILT_<TIER>
+# definitions and the generated umbrella's include path. Those live on an internal interface
+# target on purpose, so they reach the library and the tests but not consumers.
+target_link_libraries(test_spaces PUBLIC gtest VectorSimilarity vecsim_spaces_manifest)
 target_link_libraries(test_common PUBLIC gtest VectorSimilarity)
 target_link_libraries(test_components PUBLIC gtest VectorSimilarity)
 target_link_libraries(test_types PUBLIC gtest VectorSimilarity)
diff --git a/tests/unit/test_spaces.cpp b/tests/unit/test_spaces.cpp
index 18ef7a625..fdb3ea3f1 100644
--- a/tests/unit/test_spaces.cpp
+++ b/tests/unit/test_spaces.cpp
@@ -14,6 +14,7 @@
 #include <random>
 #include <cmath>
 #include <limits>
+#include <vector>
 
 #include "gtest/gtest.h"
 #include "VecSim/spaces/space_includes.h"
@@ -23,6 +24,7 @@
 #include "VecSim/types/bfloat16.h"
 #include "VecSim/spaces/IP_space.h"
 #include "VecSim/spaces/L2_space.h"
+#include "VecSim/spaces/tier_info.h"
 #include "VecSim/types/float16.h"
 #include "VecSim/types/sq8.h"
 #include "VecSim/spaces/functions/AVX512F.h"
@@ -1427,12 +1429,11 @@ TEST_P(FP16SpacesOptimizationTestAdvanced, FP16InnerProductTestAdv) {
     std::mt19937 gen(42);
     std::uniform_real_distribution<> dis(-0.99, 0.99);
 
-#if defined(CPU_FEATURES_ARCH_AARCH64) && defined(__GNUC__) && (__GNUC__ < 13)
-    // https://github.com/pytorch/executorch/issues/6844
-    __fp16 baseline = 0;
-#else
-    _Float16 baseline = 0;
-#endif
+    // Accumulate the reference in float, exactly as FP16_InnerProduct does: it widens each stored
+    // half with FP16_to_FP32 and sums into a float. A _Float16 accumulator here would make this
+    // test agree with any kernel that also accumulates in half precision, which is how an fp16
+    // accumulator in these tiers went unnoticed.
+    float baseline = 0;
 
     for (size_t i = 0; i < dim; i++) {
         float val1 = (dis(gen));
@@ -1440,9 +1441,9 @@ TEST_P(FP16SpacesOptimizationTestAdvanced, FP16InnerProductTestAdv) {
         v1[i] = vecsim_types::FP32_to_FP16((val1));
         v2[i] = vecsim_types::FP32_to_FP16((val2));
 
-        baseline += static_cast<decltype(baseline)>(val1) * static_cast<decltype(baseline)>(val2);
+        baseline += vecsim_types::FP16_to_FP32(v1[i]) * vecsim_types::FP16_to_FP32(v2[i]);
     }
-    baseline = decltype(baseline)(1) - baseline;
+    baseline = 1.0f - baseline;
 
     auto expected_alignment = [](size_t reg_bit_size, size_t dim) {
         size_t elements_in_reg = reg_bit_size / sizeof(float16) / 8;
@@ -1532,14 +1533,17 @@ TEST_P(FP16SpacesOptimizationTestAdvanced, FP16L2SqrTestAdv) {
         std::mt19937 gen(42);
         std::uniform_real_distribution<float> dis(-0.99f, 0.99f);
 
-        _Float16 baseline = 0;
+        // Accumulate the reference in float, exactly as FP16_L2Sqr does: widen both stored halves
+        // with FP16_to_FP32, subtract in float, and sum into a float. See the note on the inner
+        // product baseline above.
+        float baseline = 0;
         for (size_t i = 0; i < dim; i++) {
             float val1 = (dis(gen));
             float val2 = (dis(gen));
             v1[i] = vecsim_types::FP32_to_FP16((val1));
             v2[i] = vecsim_types::FP32_to_FP16((val2));
 
-            _Float16 diff = static_cast<_Float16>(val1) - static_cast<_Float16>(val2);
+            float diff = vecsim_types::FP16_to_FP32(v1[i]) - vecsim_types::FP16_to_FP32(v2[i]);
             baseline += diff * diff;
         }
 
@@ -1570,6 +1574,118 @@ INSTANTIATE_TEST_SUITE_P(, FP16SpacesOptimizationTestAdvanced,
 
 #endif // defined(OPT_AVX512_FP16_VL) || defined(CPU_FEATURES_ARCH_AARCH64)
 
+// Regression test for the accumulator width of the float16 SIMD kernels.
+//
+// The randomized tests above cannot catch a half precision accumulator. They draw values from
+// [-0.99, 0.99] and allow 1% relative error, and a kernel that accumulates in fp16 stays inside
+// that budget: its worst error over dim 32..256 on that distribution is about 0.54%. These inputs
+// separate the two implementations by a wide margin instead. 65504 is the largest finite fp16
+// value, so summing even a handful of squared differences of 200 pushes a half precision
+// accumulator past it and the result becomes infinity, while every value here is exactly
+// representable in fp32 and the expected total is exact.
+//
+// The public choosers are called without a feature override, so whichever tier this CPU selects is
+// the one under test, and the scalar path is covered on machines with no SIMD tier at all.
+TEST(FP16SpacesTest, LargeValuesDoNotOverflowTheAccumulator) {
+    // Exactly `dim` elements, no padding: the residual paths issue full-width loads that overlap
+    // the prefix rather than reading past the end, so at dim=35 the x86 kernel covers 0..15, then
+    // 3..18 and 19..34. Tight buffers keep ASan's bounds checking meaningful here.
+    for (size_t dim : {32UL, 35UL, 40UL, 64UL, 128UL}) {
+        std::vector<float16> v1(dim, vecsim_types::FP32_to_FP16(0.0f));
+        std::vector<float16> v2(dim, vecsim_types::FP32_to_FP16(0.0f));
+        for (size_t i = 0; i < dim; i++) {
+            v1[i] = vecsim_types::FP32_to_FP16(200.0f);
+        }
+
+        // L2: v2 is all zeros, so the distance is dim * 200^2.
+        const float expected_l2 = static_cast<float>(dim) * 200.0f * 200.0f;
+        const float l2 = L2_FP16_GetDistFunc(dim)(v1.data(), v2.data(), dim);
+        ASSERT_TRUE(std::isfinite(l2)) << "L2 accumulator overflowed at dim " << dim;
+        ASSERT_NEAR(l2, expected_l2, expected_l2 * 1e-6f) << "L2 at dim " << dim;
+
+        // Inner product: both sides at 200, so the raw product sums to dim * 200^2 and the
+        // returned distance is 1 - that.
+        for (size_t i = 0; i < dim; i++) {
+            v2[i] = vecsim_types::FP32_to_FP16(200.0f);
+        }
+        const float expected_ip = 1.0f - static_cast<float>(dim) * 200.0f * 200.0f;
+        const float ip = IP_FP16_GetDistFunc(dim)(v1.data(), v2.data(), dim);
+        ASSERT_TRUE(std::isfinite(ip)) << "IP accumulator overflowed at dim " << dim;
+        ASSERT_NEAR(ip, expected_ip, std::abs(expected_ip) * 1e-6f) << "IP at dim " << dim;
+    }
+}
+
+// TierInfo reads two columns of isa_tiers.def that must never be conflated: FLAGS_FROM, which
+// builds the compile command, and GUARANTEES, which builds the runtime predicate. A flag fragment
+// expands to a compiler-defined bundle, so a predicate derived from flags can claim support the
+// hardware does not have. These tests pin the separation on the real manifest rows where the two
+// columns differ, rather than on a synthetic tier, so they also document why those rows differ.
+TEST(TierInfoTest, SupportedFoldsGuaranteesNotFlags) {
+    spaces::FeaturesType f;
+    std::memset(&f, 0, sizeof(f));
+
+#if defined(CPU_FEATURES_ARCH_AARCH64)
+    // NEON_FHM: FLAGS_FROM is (ASIMDFHM), GUARANTEES is (ASIMDHP, ASIMDFHM). The tier is compiled
+    // at +fp16fml, and FEAT_FHM is optional in armv8.2-a, so a core can have FP16 without FHM.
+    // Deriving the predicate from the flags would accept asimdfhm alone and execute FMLAL on a core
+    // that lacks it.
+    f.asimdfhm = 1;
+    f.asimdhp = 0;
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::NEON_FHM>::supported(f))
+        << "asimdfhm alone must not select NEON_FHM: GUARANTEES also requires asimdhp";
+    f.asimdhp = 1;
+    EXPECT_TRUE(spaces::TierInfo<spaces::Tier::NEON_FHM>::supported(f));
+
+    // A tier of the other architecture is never supported, whatever the mask says.
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::AVX2>::supported(f));
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::AVX2>::compiled);
+#else
+    // SSE4_F16C: compiled "-msse4.1 -mavx -mf16c" and predicated on sse4_1 && f16c && avx, because
+    // -mf16c is VEX-encoded and puts AVX-state instructions in reach.
+    f.sse4_1 = 1;
+    f.f16c = 1;
+    f.avx = 0;
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::SSE4_F16C>::supported(f))
+        << "sse4_1 and f16c without avx must not select a tier compiled with -mavx";
+    f.avx = 1;
+    EXPECT_TRUE(spaces::TierInfo<spaces::Tier::SSE4_F16C>::supported(f));
+
+    // The VNNI tier is compiled with -mavx512vl, so avx512vl belongs in its predicate. Six legacy
+    // dispatch sites omitted it.
+    std::memset(&f, 0, sizeof(f));
+    f.avx512f = 1;
+    f.avx512bw = 1;
+    f.avx512vnni = 1;
+    f.avx512vl = 0;
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::AVX512_F_BW_VL_VNNI>::supported(f));
+    f.avx512vl = 1;
+    EXPECT_TRUE(spaces::TierInfo<spaces::Tier::AVX512_F_BW_VL_VNNI>::supported(f));
+
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::NEON>::supported(f));
+    EXPECT_FALSE(spaces::TierInfo<spaces::Tier::NEON>::compiled);
+#endif
+}
+
+// Availability is defined for every tier on every build, not only for the ones that compiled, so
+// `if constexpr (TierInfo<T>::compiled)` is well formed for all of them. A positive-only macro
+// would make that expression fail to compile for the tiers it matters most for.
+TEST(TierInfoTest, EveryTierHasAnAvailabilityValue) {
+    constexpr bool all_defined = spaces::TierInfo<spaces::Tier::AVX2>::compiled ||
+                                 !spaces::TierInfo<spaces::Tier::AVX2>::compiled;
+    EXPECT_TRUE(all_defined);
+    // On this build exactly one architecture's tiers can be compiled.
+    EXPECT_EQ(spaces::TierInfo<spaces::Tier::NEON>::arch_of, spaces::Arch::ARM);
+    EXPECT_EQ(spaces::TierInfo<spaces::Tier::AVX2>::arch_of, spaces::Arch::X86);
+    if (spaces::TierInfo<spaces::Tier::NEON>::compiled) {
+        EXPECT_FALSE(spaces::TierInfo<spaces::Tier::AVX2>::compiled);
+    }
+    // Priorities order the tiers within an architecture.
+    EXPECT_GT(spaces::TierInfo<spaces::Tier::AVX2>::priority_of,
+              spaces::TierInfo<spaces::Tier::SSE4>::priority_of);
+    EXPECT_GT(spaces::TierInfo<spaces::Tier::SVE2>::priority_of,
+              spaces::TierInfo<spaces::Tier::NEON>::priority_of);
+}
+
 class INT8SpacesOptimizationTest : public testing::TestWithParam<size_t> {};
 
 TEST_P(INT8SpacesOptimizationTest, INT8L2SqrTest) {
@@ -2356,7 +2472,8 @@ TEST_P(SQ8_FP32_SpacesOptimizationTest, SQ8_FP32_L2SqrTest) {
     float baseline = SQ8_FP32_L2Sqr(v2_compressed.data(), v1_orig.data(), dim);
 // Test different optimizations based on CPU features
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         arch_opt_func = L2_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_FP32_L2_implementation_AVX512F_BW_VL_VNNI(dim))
@@ -2482,7 +2599,8 @@ TEST_P(SQ8_FP32_SpacesOptimizationTest, SQ8_FP32_InnerProductTest) {
 
 // Test different optimizations based on CPU features
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         arch_opt_func = IP_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_FP32_IP_implementation_AVX512F_BW_VL_VNNI(dim))
@@ -2633,7 +2751,8 @@ TEST_P(SQ8_FP32_SpacesOptimizationTest, SQ8_FP32_CosineTest) {
 
 // Test different optimizations based on CPU features
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         arch_opt_func = Cosine_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_FP32_Cosine_implementation_AVX512F_BW_VL_VNNI(dim))
@@ -2745,7 +2864,8 @@ TEST(SQ8_FP32_EdgeCases, SelfDistanceCosine) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_quantized.data(), v_orig.data(), dim);
@@ -2846,7 +2966,8 @@ TEST(SQ8_FP32_EdgeCases, SelfDistanceL2) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = L2_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_quantized.data(), v_orig.data(), dim);
@@ -2955,7 +3076,8 @@ TEST(SQ8_FP32_EdgeCases, CosineSymmetryTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         float cos_12 = arch_opt_func(v2_quantized.data(), v1_fp32.data(), dim);
@@ -3022,7 +3144,8 @@ TEST(SQ8_FP32_EdgeCases, CosineZeroVectorTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_nonzero_quantized.data(), v_zero.data(), dim);
@@ -3102,7 +3225,8 @@ TEST(SQ8_FP32_EdgeCases, CosineConstantVectorTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_const_quantized.data(), v_query.data(), dim);
@@ -3182,7 +3306,8 @@ TEST(SQ8_FP32_EdgeCases, CosineExtremeValuesTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_FP32_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v2_quantized.data(), v1.data(), dim);
@@ -3372,7 +3497,7 @@ TEST_P(SQ8_FP16_SpacesOptimizationTest, SQ8_FP16_L2SqrTest) {
     }
 #endif
 #ifdef OPT_NEON_FHM
-    if (optimization.asimdfhm) {
+    if (optimization.asimdhp && optimization.asimdfhm) {
         unsigned char alignment = 0;
         arch_opt_func = L2_SQ8_FP16_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_FP16_L2_implementation_NEON_FHM(dim))
@@ -3498,7 +3623,7 @@ TEST_P(SQ8_FP16_SpacesOptimizationTest, SQ8_FP16_InnerProductTest) {
     }
 #endif
 #ifdef OPT_NEON_FHM
-    if (optimization.asimdfhm) {
+    if (optimization.asimdhp && optimization.asimdfhm) {
         unsigned char alignment = 0;
         arch_opt_func = IP_SQ8_FP16_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_FP16_IP_implementation_NEON_FHM(dim))
@@ -3624,7 +3749,7 @@ TEST_P(SQ8_FP16_SpacesOptimizationTest, SQ8_FP16_CosineTest) {
     }
 #endif
 #ifdef OPT_NEON_FHM
-    if (optimization.asimdfhm) {
+    if (optimization.asimdhp && optimization.asimdfhm) {
         unsigned char alignment = 0;
         arch_opt_func = Cosine_SQ8_FP16_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_FP16_Cosine_implementation_NEON_FHM(dim))
@@ -3925,7 +4050,8 @@ TEST_P(SQ8_SQ8_SpacesOptimizationTest, SQ8_SQ8_InnerProductTest) {
 #endif
 
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         arch_opt_func = IP_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_SQ8_IP_implementation_AVX512F_BW_VL_VNNI(dim))
@@ -4008,7 +4134,8 @@ TEST_P(SQ8_SQ8_SpacesOptimizationTest, SQ8_SQ8_CosineTest) {
 #endif
 
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         arch_opt_func = Cosine_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_SQ8_Cosine_implementation_AVX512F_BW_VL_VNNI(dim))
@@ -4091,7 +4218,8 @@ TEST_P(SQ8_SQ8_SpacesOptimizationTest, SQ8_SQ8_L2SqrTest) {
 #endif
 
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         arch_opt_func = L2_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         ASSERT_EQ(arch_opt_func, Choose_SQ8_SQ8_L2_implementation_AVX512F_BW_VL_VNNI(dim))
@@ -4170,7 +4298,8 @@ TEST(SQ8_SQ8_EdgeCases, SelfDistanceCosine) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_quantized.data(), v_quantized.data(), dim);
@@ -4242,7 +4371,8 @@ TEST(SQ8_SQ8_EdgeCases, CosineSymmetryTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float cos_12 = arch_opt_func(v1_quantized.data(), v2_quantized.data(), dim);
@@ -4310,7 +4440,8 @@ TEST(SQ8_SQ8_EdgeCases, CosineZeroVectorTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_zero_quantized.data(), v_nonzero_quantized.data(), dim);
@@ -4382,7 +4513,8 @@ TEST(SQ8_SQ8_EdgeCases, CosineConstantVectorTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_const_quantized.data(), v_random_quantized.data(), dim);
@@ -4463,7 +4595,8 @@ TEST(SQ8_SQ8_EdgeCases, CosineExtremeValuesTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = Cosine_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v1_quantized.data(), v2_quantized.data(), dim);
@@ -4532,7 +4665,8 @@ TEST(SQ8_SQ8_EdgeCases, SelfDistanceL2) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = L2_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_quantized.data(), v_quantized.data(), dim);
@@ -4604,7 +4738,8 @@ TEST(SQ8_SQ8_EdgeCases, L2SymmetryTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = L2_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float l2_12 = arch_opt_func(v1_quantized.data(), v2_quantized.data(), dim);
@@ -4672,7 +4807,8 @@ TEST(SQ8_SQ8_EdgeCases, L2ZeroVectorTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = L2_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_zero_quantized.data(), v_nonzero_quantized.data(), dim);
@@ -4743,7 +4879,8 @@ TEST(SQ8_SQ8_EdgeCases, L2ConstantVectorTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = L2_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v_const_quantized.data(), v_random_quantized.data(), dim);
@@ -4817,7 +4954,8 @@ TEST(SQ8_SQ8_EdgeCases, L2ExtremeValuesTest) {
     }
 #endif
 #ifdef OPT_AVX512_F_BW_VL_VNNI
-    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vnni) {
+    if (optimization.avx512f && optimization.avx512bw && optimization.avx512vl &&
+        optimization.avx512vnni) {
         unsigned char alignment = 0;
         auto arch_opt_func = L2_SQ8_SQ8_GetDistFunc(dim, &alignment, &optimization);
         float result = arch_opt_func(v1_quantized.data(), v2_quantized.data(), dim);
@@ -4915,3 +5053,143 @@ TEST_F(SpacesTest, SQ8_SQ8_DispatcherAlignmentHints) {
     check("Cosine", &spaces::Cosine_SQ8_SQ8_GetDistFunc);
 }
 #endif // CPU_FEATURES_ARCH_X86_64
+
+// Enforce the pure-bitfield layout assumption that spaces::intersectWithDetectedFeatures (see
+// spaces/spaces.h) relies on: the platform's cpu_features Features struct must be composed
+// entirely of `int <name> : 1;` bitfields with no other members, so a byte-wise AND over the
+// struct's object representation is equivalent to a per-feature logical AND. We do not hand-list
+// the fields, since that would rot the moment cpu_features adds one; instead we walk every enum
+// value via cpu_features' own enum-value reader and compare it against the field-wise AND. If
+// cpu_features ever adds a non-bitfield member, the byte-wise AND diverges from this field-wise
+// truth and the test below fails.
+#ifdef CPU_FEATURES_ARCH_X86_64
+TEST_F(SpacesTest, CpuFeatureIntersectionX86) {
+    auto detected = getCpuOptimizationFeatures();
+
+    // An all-detected mask ANDed with a mask that clears one feature yields that feature cleared.
+    auto clears_one = detected;
+    clears_one.sse = 0;
+    auto cleared_result = intersectWithDetectedFeatures(clears_one, detected);
+    ASSERT_EQ(cpu_features::GetX86FeaturesEnumValue(&cleared_result, cpu_features::X86_SSE), 0);
+
+    // This is the hole being closed: build a detected set that (synthetically) lacks a feature,
+    // and an override that claims it anyway. The intersection must keep it clear regardless.
+    auto lacks_avx512f = detected;
+    lacks_avx512f.avx512f = 0;
+    auto claims_avx512f = lacks_avx512f;
+    claims_avx512f.avx512f = 1;
+    auto claimed_result = intersectWithDetectedFeatures(claims_avx512f, lacks_avx512f);
+    ASSERT_EQ(cpu_features::GetX86FeaturesEnumValue(&claimed_result, cpu_features::X86_AVX512F), 0);
+
+    // General correctness for both scenarios above: every feature in the intersection must equal
+    // the logical AND of the two masks it was built from.
+    // GetX86FeaturesEnumValue returns the raw `int <name> : 1;` field, which for a set signed
+    // 1-bit field reads back as -1 (sign-extended), not 1. Compare as bool so the sign
+    // representation of "set" does not matter, only whether the bit is set.
+    for (int i = 0; i < cpu_features::X86_LAST_; i++) {
+        auto value = static_cast<cpu_features::X86FeaturesEnum>(i);
+        bool expected_cleared = cpu_features::GetX86FeaturesEnumValue(&clears_one, value) &&
+                                cpu_features::GetX86FeaturesEnumValue(&detected, value);
+        ASSERT_EQ(static_cast<bool>(cpu_features::GetX86FeaturesEnumValue(&cleared_result, value)),
+                  expected_cleared)
+            << "feature " << cpu_features::GetX86FeaturesEnumName(value);
+
+        bool expected_claimed = cpu_features::GetX86FeaturesEnumValue(&claims_avx512f, value) &&
+                                cpu_features::GetX86FeaturesEnumValue(&lacks_avx512f, value);
+        ASSERT_EQ(static_cast<bool>(cpu_features::GetX86FeaturesEnumValue(&claimed_result, value)),
+                  expected_claimed)
+            << "feature " << cpu_features::GetX86FeaturesEnumName(value);
+    }
+}
+#endif // CPU_FEATURES_ARCH_X86_64
+
+#ifdef CPU_FEATURES_ARCH_AARCH64
+TEST_F(SpacesTest, CpuFeatureIntersectionAarch64) {
+    auto detected = getCpuOptimizationFeatures();
+
+    // An all-detected mask ANDed with a mask that clears one feature yields that feature cleared.
+    auto clears_one = detected;
+    clears_one.asimd = 0;
+    auto cleared_result = intersectWithDetectedFeatures(clears_one, detected);
+    ASSERT_EQ(
+        cpu_features::GetAarch64FeaturesEnumValue(&cleared_result, cpu_features::AARCH64_ASIMD), 0);
+
+    // This is the hole being closed: build a detected set that (synthetically) lacks a feature,
+    // and an override that claims it anyway. The intersection must keep it clear regardless.
+    auto lacks_sve = detected;
+    lacks_sve.sve = 0;
+    auto claims_sve = lacks_sve;
+    claims_sve.sve = 1;
+    auto claimed_result = intersectWithDetectedFeatures(claims_sve, lacks_sve);
+    ASSERT_EQ(cpu_features::GetAarch64FeaturesEnumValue(&claimed_result, cpu_features::AARCH64_SVE),
+              0);
+
+    // General correctness for both scenarios above: every feature in the intersection must equal
+    // the logical AND of the two masks it was built from.
+    // GetAarch64FeaturesEnumValue returns the raw `int <name> : 1;` field, which for a set signed
+    // 1-bit field reads back as -1 (sign-extended), not 1. Compare as bool so the sign
+    // representation of "set" does not matter, only whether the bit is set.
+    for (int i = 0; i < cpu_features::AARCH64_LAST_; i++) {
+        auto value = static_cast<cpu_features::Aarch64FeaturesEnum>(i);
+        bool expected_cleared = cpu_features::GetAarch64FeaturesEnumValue(&clears_one, value) &&
+                                cpu_features::GetAarch64FeaturesEnumValue(&detected, value);
+        ASSERT_EQ(
+            static_cast<bool>(cpu_features::GetAarch64FeaturesEnumValue(&cleared_result, value)),
+            expected_cleared)
+            << "feature " << cpu_features::GetAarch64FeaturesEnumName(value);
+
+        bool expected_claimed = cpu_features::GetAarch64FeaturesEnumValue(&claims_sve, value) &&
+                                cpu_features::GetAarch64FeaturesEnumValue(&lacks_sve, value);
+        ASSERT_EQ(
+            static_cast<bool>(cpu_features::GetAarch64FeaturesEnumValue(&claimed_result, value)),
+            expected_claimed)
+            << "feature " << cpu_features::GetAarch64FeaturesEnumName(value);
+    }
+}
+#endif // CPU_FEATURES_ARCH_AARCH64
+
+// The CpuFeatureIntersection* tests above call intersectWithDetectedFeatures() directly; they do
+// not exercise getCpuOptimizationFeatures(&mask), which is the actual entry point every real
+// caller (and every chooser in spaces.cpp) goes through, and the function whose behavior this
+// series of fixes changed. Cover that entry point here: a mask claiming every feature still
+// cannot make the result report a feature the live hardware does not have, since
+// getCpuOptimizationFeatures() always intersects the passed-in mask with a fresh read of the
+// real detected features, not with whatever the caller believes is detected.
+#ifdef CPU_FEATURES_ARCH_X86_64
+TEST_F(SpacesTest, GetCpuOptimizationFeaturesAppliesMaskX86) {
+    auto detected = getCpuOptimizationFeatures();
+
+    auto all_claimed = detected;
+    std::memset(&all_claimed, 0xFF, sizeof(all_claimed));
+
+    auto result = getCpuOptimizationFeatures(&all_claimed);
+    for (int i = 0; i < cpu_features::X86_LAST_; i++) {
+        auto value = static_cast<cpu_features::X86FeaturesEnum>(i);
+        bool detected_bit =
+            static_cast<bool>(cpu_features::GetX86FeaturesEnumValue(&detected, value));
+        bool result_bit = static_cast<bool>(cpu_features::GetX86FeaturesEnumValue(&result, value));
+        ASSERT_EQ(result_bit, detected_bit)
+            << "feature " << cpu_features::GetX86FeaturesEnumName(value);
+    }
+}
+#endif // CPU_FEATURES_ARCH_X86_64
+
+#ifdef CPU_FEATURES_ARCH_AARCH64
+TEST_F(SpacesTest, GetCpuOptimizationFeaturesAppliesMaskAarch64) {
+    auto detected = getCpuOptimizationFeatures();
+
+    auto all_claimed = detected;
+    std::memset(&all_claimed, 0xFF, sizeof(all_claimed));
+
+    auto result = getCpuOptimizationFeatures(&all_claimed);
+    for (int i = 0; i < cpu_features::AARCH64_LAST_; i++) {
+        auto value = static_cast<cpu_features::Aarch64FeaturesEnum>(i);
+        bool detected_bit =
+            static_cast<bool>(cpu_features::GetAarch64FeaturesEnumValue(&detected, value));
+        bool result_bit =
+            static_cast<bool>(cpu_features::GetAarch64FeaturesEnumValue(&result, value));
+        ASSERT_EQ(result_bit, detected_bit)
+            << "feature " << cpu_features::GetAarch64FeaturesEnumName(value);
+    }
+}
+#endif // CPU_FEATURES_ARCH_AARCH64