-
Notifications
You must be signed in to change notification settings - Fork 0
Expand file tree
/
Copy pathvm_dispatch_compare.asm
More file actions
772 lines (641 loc) · 15.6 KB
/
Copy pathvm_dispatch_compare.asm
File metadata and controls
772 lines (641 loc) · 15.6 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
.eqv OP_PUSH 0
.eqv OP_ADD 1
.eqv OP_SUB 2
.eqv OP_LOAD 3
.eqv OP_STORE 4
.eqv OP_HALT 5
.eqv ITERATIONS 1000
.data
.align 2
intro_msg: .asciiz "Mini-VM: comparador de dispatch (switch x direct threading)\nObservacao: o demo executa uma passada de cada interpretador; o relatorio usa apenas o benchmark.\n"
layout_title: .asciiz "\n=== LAYOUT / ENDERECOS ===\n"
demo_switch_title: .asciiz "\n=== DEMO 1 / SWITCH DISPATCH ===\nUse Step (F7) em switch_dispatch para ver o PC passar por varios beq antes do handler.\n"
demo_thread_title: .asciiz "\n=== DEMO 2 / DIRECT THREADING ===\nUse Step (F7) em thread_dispatch para ver o salto indireto ir direto ao handler.\n"
bench_switch_title: .asciiz "\n=== BENCHMARK / SWITCH DISPATCH ===\n"
bench_thread_title: .asciiz "\n=== BENCHMARK / DIRECT THREADING ===\n"
report_title: .asciiz "\n============================================================\nRELATORIO COMPARATIVO DE DISPATCH\n============================================================\n"
switch_section_title: .asciiz "Versao 1 - Switch Dispatch\n"
thread_section_title: .asciiz "\nVersao 2 - Direct Threading\n"
delta_section_title: .asciiz "\nDelta e conclusao\n"
msg_dispatch_note: .asciiz "Contador de branches mede apenas a selecao do dispatch (beq no switch, jr indireto no threading).\n\n"
msg_vm_stack_base: .asciiz "Base da pilha virtual: "
msg_vm_mem_base: .asciiz "Base da memoria virtual: "
msg_switch_dispatch_base: .asciiz "Switch dispatch loop: "
msg_switch_push_addr: .asciiz "Switch handler PUSH: "
msg_switch_add_addr: .asciiz "Switch handler ADD: "
msg_switch_sub_addr: .asciiz "Switch handler SUB: "
msg_switch_load_addr: .asciiz "Switch handler LOAD: "
msg_switch_store_addr: .asciiz "Switch handler STORE: "
msg_switch_halt_addr: .asciiz "Switch handler HALT: "
msg_thread_dispatch_base: .asciiz "Thread dispatch loop: "
msg_thread_table_base: .asciiz "Base da jump table: "
msg_thread_slot0: .asciiz "thread_table[0] slot: "
msg_thread_slot1: .asciiz "thread_table[1] slot: "
msg_thread_slot2: .asciiz "thread_table[2] slot: "
msg_thread_slot3: .asciiz "thread_table[3] slot: "
msg_thread_slot4: .asciiz "thread_table[4] slot: "
msg_thread_slot5: .asciiz "thread_table[5] slot: "
msg_thread_push_addr: .asciiz "Thread handler PUSH: "
msg_thread_add_addr: .asciiz "Thread handler ADD: "
msg_thread_sub_addr: .asciiz "Thread handler SUB: "
msg_thread_load_addr: .asciiz "Thread handler LOAD: "
msg_thread_store_addr: .asciiz "Thread handler STORE: "
msg_thread_halt_addr: .asciiz "Thread handler HALT: "
msg_instr_count: .asciiz " Instrucoes de bytecode executadas: "
msg_branch_count: .asciiz " Branches de dispatch executados: "
msg_dispatch_addr: .asciiz " Endereco do dispatch loop: "
msg_jump_table_addr: .asciiz " Endereco base da jump table: "
msg_handler_add: .asciiz " Handler ADD: "
msg_handler_sub: .asciiz " Handler SUB: "
msg_result_mem: .asciiz " Resultado final em vm_mem[0]: "
msg_result_top: .asciiz " Topo final da pilha: "
msg_delta_instr: .asciiz " Delta instrucoes (switch - threading): "
msg_delta_branches: .asciiz " Delta branches (switch - threading): "
msg_conclusion_prefix: .asciiz " Conclusao estatica: switch usa "
msg_conclusion_suffix: .asciiz " branches de dispatch a mais neste benchmark.\n"
msg_conclusion_arch: .asciiz " Conclusao arquitetural: a reducao estrutural de branches existe, mas MARS mede fluxo funcional; use o binario C com perf para defender equivalencia pratica em hardware real.\n"
msg_demo_done: .asciiz "Demo concluido.\n"
msg_bench_done: .asciiz "Benchmark concluido.\n"
newline: .asciiz "\n"
hex_digits: .asciiz "0123456789ABCDEF"
# Bytecode: PUSH 10 / PUSH 20 / ADD / PUSH 5 / SUB / STORE 0 / LOAD 0 / HALT
program_demo:
.word OP_PUSH, 10
.word OP_PUSH, 20
.word OP_ADD
.word OP_PUSH, 5
.word OP_SUB
.word OP_STORE, 0
.word OP_LOAD, 0
.word OP_HALT
program_bench:
.word OP_PUSH, 10
.word OP_PUSH, 20
.word OP_ADD
.word OP_PUSH, 5
.word OP_SUB
.word OP_STORE, 0
.word OP_LOAD, 0
.word OP_HALT
.align 2
vm_stack: .space 64
vm_mem: .space 16
# Jump table para a versao 2.
thread_table:
.word th_push
.word th_add
.word th_sub
.word th_load
.word th_store
.word th_halt
# Armazenamento dos resultados para o relatorio final.
switch_instr_saved: .word 0
switch_branch_saved: .word 0
switch_mem_saved: .word 0
switch_top_saved: .word 0
thread_instr_saved: .word 0
thread_branch_saved: .word 0
thread_mem_saved: .word 0
thread_top_saved: .word 0
.text
.globl main
main:
la $a0, intro_msg
li $v0, 4
syscall
jal print_layout
nop
la $a0, demo_switch_title
li $v0, 4
syscall
li $s7, 0
li $s6, 0
la $a0, program_demo
jal run_switch_program
nop
la $a0, msg_demo_done
li $v0, 4
syscall
la $a0, demo_thread_title
li $v0, 4
syscall
li $s7, 0
li $s6, 0
la $a0, program_demo
jal run_thread_program
nop
la $a0, msg_demo_done
li $v0, 4
syscall
la $a0, bench_switch_title
li $v0, 4
syscall
jal run_switch_benchmark
nop
sw $s7, switch_instr_saved
sw $s6, switch_branch_saved
sw $v0, switch_mem_saved
sw $v1, switch_top_saved
la $a0, msg_bench_done
li $v0, 4
syscall
la $a0, bench_thread_title
li $v0, 4
syscall
jal run_thread_benchmark
nop
sw $s7, thread_instr_saved
sw $s6, thread_branch_saved
sw $v0, thread_mem_saved
sw $v1, thread_top_saved
la $a0, msg_bench_done
li $v0, 4
syscall
jal print_report
nop
li $v0, 10
syscall
# ------------------------------------------------------------
# Helpers de impressao
# ------------------------------------------------------------
print_named_int:
addiu $sp, $sp, -8
sw $ra, 4($sp)
sw $a1, 0($sp)
li $v0, 4
syscall
lw $a0, 0($sp)
li $v0, 1
syscall
la $a0, newline
li $v0, 4
syscall
lw $ra, 4($sp)
addiu $sp, $sp, 8
jr $ra
nop
print_named_hex:
addiu $sp, $sp, -8
sw $ra, 4($sp)
sw $a1, 0($sp)
li $v0, 4
syscall
lw $a0, 0($sp)
jal print_hex32
nop
la $a0, newline
li $v0, 4
syscall
lw $ra, 4($sp)
addiu $sp, $sp, 8
jr $ra
nop
print_hex32:
move $t0, $a0
la $t3, hex_digits
li $v0, 11
li $a0, '0'
syscall
li $a0, 'x'
syscall
li $t1, 28
print_hex32_loop:
srlv $t2, $t0, $t1
andi $t2, $t2, 0x000F
addu $t4, $t3, $t2
lbu $a0, 0($t4)
li $v0, 11
syscall
addiu $t1, $t1, -4
bgez $t1, print_hex32_loop
nop
jr $ra
nop
# ------------------------------------------------------------
# Impressao do layout de memoria / enderecos
# ------------------------------------------------------------
print_layout:
addiu $sp, $sp, -4
sw $ra, 0($sp)
la $a0, layout_title
li $v0, 4
syscall
la $a0, msg_vm_stack_base
la $a1, vm_stack
jal print_named_hex
nop
la $a0, msg_vm_mem_base
la $a1, vm_mem
jal print_named_hex
nop
la $a0, msg_switch_dispatch_base
la $a1, switch_dispatch
jal print_named_hex
nop
la $a0, msg_switch_push_addr
la $a1, switch_push
jal print_named_hex
nop
la $a0, msg_switch_add_addr
la $a1, switch_add
jal print_named_hex
nop
la $a0, msg_switch_sub_addr
la $a1, switch_sub
jal print_named_hex
nop
la $a0, msg_switch_load_addr
la $a1, switch_load
jal print_named_hex
nop
la $a0, msg_switch_store_addr
la $a1, switch_store
jal print_named_hex
nop
la $a0, msg_switch_halt_addr
la $a1, switch_halt
jal print_named_hex
nop
la $a0, msg_thread_dispatch_base
la $a1, thread_dispatch
jal print_named_hex
nop
la $a0, msg_thread_table_base
la $a1, thread_table
jal print_named_hex
nop
la $a0, msg_thread_slot0
la $a1, thread_table
jal print_named_hex
nop
la $a0, msg_thread_slot1
la $t0, thread_table
addiu $a1, $t0, 4
jal print_named_hex
nop
la $a0, msg_thread_slot2
la $t0, thread_table
addiu $a1, $t0, 8
jal print_named_hex
nop
la $a0, msg_thread_slot3
la $t0, thread_table
addiu $a1, $t0, 12
jal print_named_hex
nop
la $a0, msg_thread_slot4
la $t0, thread_table
addiu $a1, $t0, 16
jal print_named_hex
nop
la $a0, msg_thread_slot5
la $t0, thread_table
addiu $a1, $t0, 20
jal print_named_hex
nop
la $a0, msg_thread_push_addr
la $a1, th_push
jal print_named_hex
nop
la $a0, msg_thread_add_addr
la $a1, th_add
jal print_named_hex
nop
la $a0, msg_thread_sub_addr
la $a1, th_sub
jal print_named_hex
nop
la $a0, msg_thread_load_addr
la $a1, th_load
jal print_named_hex
nop
la $a0, msg_thread_store_addr
la $a1, th_store
jal print_named_hex
nop
la $a0, msg_thread_halt_addr
la $a1, th_halt
jal print_named_hex
nop
la $a0, newline
li $v0, 4
syscall
lw $ra, 0($sp)
addiu $sp, $sp, 4
jr $ra
nop
# ------------------------------------------------------------
# Benchmark loops
# ------------------------------------------------------------
run_switch_benchmark:
addiu $sp, $sp, -4
sw $ra, 0($sp)
switch_benchmark_start:
li $s7, 0
li $s6, 0
li $s3, ITERATIONS
switch_benchmark_loop:
beqz $s3, switch_benchmark_end
nop
la $a0, program_bench
jal run_switch_program
nop
addiu $s3, $s3, -1
j switch_benchmark_loop
nop
switch_benchmark_end:
lw $ra, 0($sp)
addiu $sp, $sp, 4
jr $ra
nop
run_thread_benchmark:
addiu $sp, $sp, -4
sw $ra, 0($sp)
thread_benchmark_start:
li $s7, 0
li $s6, 0
li $s3, ITERATIONS
thread_benchmark_loop:
beqz $s3, thread_benchmark_end
nop
la $a0, program_bench
jal run_thread_program
nop
addiu $s3, $s3, -1
j thread_benchmark_loop
nop
thread_benchmark_end:
lw $ra, 0($sp)
addiu $sp, $sp, 4
jr $ra
nop
# ------------------------------------------------------------
# Versao 1 - Switch dispatch (cadeia de beq)
# ------------------------------------------------------------
run_switch_program:
move $s0, $a0 # ip
la $s1, vm_stack # pilha virtual
la $s2, vm_mem # memoria virtual
sw $zero, 0($s2)
switch_dispatch:
lw $t0, 0($s0)
addiu $s0, $s0, 4
addiu $s7, $s7, 1
addiu $s6, $s6, 1
li $t1, OP_PUSH
beq $t0, $t1, switch_push
nop
addiu $s6, $s6, 1
li $t1, OP_ADD
beq $t0, $t1, switch_add
nop
addiu $s6, $s6, 1
li $t1, OP_SUB
beq $t0, $t1, switch_sub
nop
addiu $s6, $s6, 1
li $t1, OP_LOAD
beq $t0, $t1, switch_load
nop
addiu $s6, $s6, 1
li $t1, OP_STORE
beq $t0, $t1, switch_store
nop
addiu $s6, $s6, 1
li $t1, OP_HALT
beq $t0, $t1, switch_halt
nop
jr $ra
nop
switch_push:
lw $t2, 0($s0)
addiu $s0, $s0, 4
sw $t2, 0($s1)
addiu $s1, $s1, 4
j switch_dispatch
nop
switch_add:
addiu $s1, $s1, -4
lw $t2, 0($s1)
addiu $s1, $s1, -4
lw $t3, 0($s1)
addu $t4, $t3, $t2
sw $t4, 0($s1)
addiu $s1, $s1, 4
j switch_dispatch
nop
switch_sub:
addiu $s1, $s1, -4
lw $t2, 0($s1)
addiu $s1, $s1, -4
lw $t3, 0($s1)
subu $t4, $t3, $t2
sw $t4, 0($s1)
addiu $s1, $s1, 4
j switch_dispatch
nop
switch_load:
lw $t2, 0($s0)
addiu $s0, $s0, 4
sll $t2, $t2, 2
addu $t3, $s2, $t2
lw $t4, 0($t3)
sw $t4, 0($s1)
addiu $s1, $s1, 4
j switch_dispatch
nop
switch_store:
lw $t2, 0($s0)
addiu $s0, $s0, 4
sll $t2, $t2, 2
addu $t3, $s2, $t2
addiu $s1, $s1, -4
lw $t4, 0($s1)
sw $t4, 0($t3)
j switch_dispatch
nop
switch_halt:
lw $v0, 0($s2)
addiu $t2, $s1, -4
lw $v1, 0($t2)
jr $ra
nop
# ------------------------------------------------------------
# Versao 2 - Direct threading (jump table + jr)
# ------------------------------------------------------------
run_thread_program:
move $s0, $a0 # ip
la $s1, vm_stack # pilha virtual
la $s2, vm_mem # memoria virtual
sw $zero, 0($s2)
thread_dispatch:
lw $t0, 0($s0)
addiu $s0, $s0, 4
addiu $s7, $s7, 1
sll $t1, $t0, 2
la $t2, thread_table
addu $t2, $t2, $t1
lw $t3, 0($t2)
addiu $s6, $s6, 1
jr $t3
nop
th_push:
lw $t4, 0($s0)
addiu $s0, $s0, 4
sw $t4, 0($s1)
addiu $s1, $s1, 4
j thread_dispatch
nop
th_add:
addiu $s1, $s1, -4
lw $t4, 0($s1)
addiu $s1, $s1, -4
lw $t5, 0($s1)
addu $t6, $t5, $t4
sw $t6, 0($s1)
addiu $s1, $s1, 4
j thread_dispatch
nop
th_sub:
addiu $s1, $s1, -4
lw $t4, 0($s1)
addiu $s1, $s1, -4
lw $t5, 0($s1)
subu $t6, $t5, $t4
sw $t6, 0($s1)
addiu $s1, $s1, 4
j thread_dispatch
nop
th_load:
lw $t4, 0($s0)
addiu $s0, $s0, 4
sll $t4, $t4, 2
addu $t5, $s2, $t4
lw $t6, 0($t5)
sw $t6, 0($s1)
addiu $s1, $s1, 4
j thread_dispatch
nop
th_store:
lw $t4, 0($s0)
addiu $s0, $s0, 4
sll $t4, $t4, 2
addu $t5, $s2, $t4
addiu $s1, $s1, -4
lw $t6, 0($s1)
sw $t6, 0($t5)
j thread_dispatch
nop
th_halt:
lw $v0, 0($s2)
addiu $t2, $s1, -4
lw $v1, 0($t2)
jr $ra
nop
# ------------------------------------------------------------
# Relatorio comparativo final
# ------------------------------------------------------------
print_report:
addiu $sp, $sp, -4
sw $ra, 0($sp)
la $a0, report_title
li $v0, 4
syscall
la $a0, msg_dispatch_note
li $v0, 4
syscall
la $a0, switch_section_title
li $v0, 4
syscall
la $a0, msg_instr_count
lw $a1, switch_instr_saved
jal print_named_int
nop
la $a0, msg_branch_count
lw $a1, switch_branch_saved
jal print_named_int
nop
la $a0, msg_dispatch_addr
la $a1, switch_dispatch
jal print_named_hex
nop
la $a0, msg_handler_add
la $a1, switch_add
jal print_named_hex
nop
la $a0, msg_handler_sub
la $a1, switch_sub
jal print_named_hex
nop
la $a0, msg_result_mem
lw $a1, switch_mem_saved
jal print_named_int
nop
la $a0, msg_result_top
lw $a1, switch_top_saved
jal print_named_int
nop
la $a0, thread_section_title
li $v0, 4
syscall
la $a0, msg_instr_count
lw $a1, thread_instr_saved
jal print_named_int
nop
la $a0, msg_branch_count
lw $a1, thread_branch_saved
jal print_named_int
nop
la $a0, msg_jump_table_addr
la $a1, thread_table
jal print_named_hex
nop
la $a0, msg_handler_add
la $a1, th_add
jal print_named_hex
nop
la $a0, msg_handler_sub
la $a1, th_sub
jal print_named_hex
nop
la $a0, msg_result_mem
lw $a1, thread_mem_saved
jal print_named_int
nop
la $a0, msg_result_top
lw $a1, thread_top_saved
jal print_named_int
nop
la $a0, delta_section_title
li $v0, 4
syscall
lw $t0, switch_instr_saved
lw $t1, thread_instr_saved
subu $t2, $t0, $t1
la $a0, msg_delta_instr
move $a1, $t2
jal print_named_int
nop
lw $t0, switch_branch_saved
lw $t1, thread_branch_saved
subu $t2, $t0, $t1
la $a0, msg_delta_branches
move $a1, $t2
jal print_named_int
nop
la $a0, msg_conclusion_prefix
li $v0, 4
syscall
move $a0, $t2
li $v0, 1
syscall
la $a0, msg_conclusion_suffix
li $v0, 4
syscall
la $a0, msg_conclusion_arch
li $v0, 4
syscall
lw $ra, 0($sp)
addiu $sp, $sp, 4
jr $ra
nop